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Notes: • The theoretical regulation affects only the real-time clock counter and 1 Hz counter. It does
not affect the stopwatch counter.
• After a value is written to the RTCACTLH.RTCTRM[6:0] bits, the theoretical regulation cor-
rection takes effect on the 1 Hz counter value at the same timing as when the 1 Hz counter
changes to 0x7f. Also an interrupt occurs depending on the counter value at this time.
10.4 Operations
10.4.1 RTCA Control
Follow the sequences shown below to set time to RTCA, to read the current time and to set alarm.
Time setting
1. Set RTCA to 12H or 24H mode using the RTCACTLL.RTC24H bit.
2. Write 1 to the RTCACTLL.RTCRUN bit to enable for the real-time clock counter to start counting up.
3. Check to see if the RTCACTLL.RTCBSY bit = 0 that indicates the counter is ready to rewrite. If the
RTCACTLL.RTCBSY bit = 1, wait until it is set to 0.
4. Write the current date and time in BCD code to the control bits listed below.
RTCASEC.RTCSH[2:0]/RTCSL[3:0] bits (second)
RTCAHUR.RTCMIH[2:0]/RTCMIL[3:0] bits (minute)
RTCAHUR.RTCHH[1:0]/RTCHL[3:0] bits (hour)
RTCAHUR.RTCAP bit (AM/PM) (effective when RTCACTLL.RTC24H bit = 0)
RTCAMON.RTCDH[1:0]/RTCDL[3:0] bits (day)
RTCAMON.RTCMOH/RTCMOL[3:0] bits (month)
RTCAYAR.RTCYH[3:0]/RTCYL[3:0] bits (year)
RTCAYAR.RTCWK[2:0] bits (day of the week)
5
Write 1 to the RTCACTLL.RTCADJ bit (execute 30-second correction) using a time signal to adjust the
time. (For more information on the 30-second correction, refer to "Real-Time Clock Counter Operations.")
6. Write 1 to the real-time clock counter interrupt flags in the RTCAINTF register to clear them.
7. Write 1 to the interrupt enable bits in the RTCAINTE register to enable real-time clock counter interrupts.
Time read
1. Check to see if the RTCACTLL.RTCBSY bit = 0. If the RTCACTLL.RTCBSY bit = 1, wait until it is set to 0.
2. Write 1 to the RTCACTLL.RTCHLD bit to suspend count-up operation of the real-time clock counter.
3. Read the date and time from the control bits listed in "Time setting, Step 4" above.
4. Write 0 to the RTCACTLL.RTCHLD bit to resume count-up operation of the real-time clock counter. If a
second count-up timing has occurred in the count hold state, the hardware corrects the second counter for
+1 second (for more information on the +1 second correction, refer to "Real-Time Clock Counter Opera-
tions").
Alarm setting
1. Write 0 to the RTCAINTE.ALARMIE bit to 0 to disable alarm interrupts.
2. Write the alarm time in BCD code to the control bits listed below (a time within 24 hours from the current
time can be specified).
RTCAALM1.RTCSHA[2:0]/RTCSLA[3:0] bits (second)
RTCAALM2.RTCMIHA[2:0]/RTCMILA[3:0] bits (minute)
RTCAALM2.RTCHHA[1:0]/RTCHLA[3:0] bits (hour)
RTCAALM2.RTCAPA bit (AM/PM) (effective when RTCACTLL.RTC24H bit = 0)
3. Write 1 to the RTCAINTF.ALARMIF bit to clear the alarm interrupt flag.
4. Write 1 to the RTCAINTE.ALARMIE bit to enable alarm interrupts.
When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Seiko Epson Corporation
10 REAL-TIME CLOCK (RTCA)
10-3
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