T16B Ch.n Counter Control Register - Epson S1C31D50 Technical Manual

17 16-BIT PWM TIMERS (T16B)
Bits 7–4 CLKDIV[3:0]
These bits select the division ratio of the T16B Ch.n operating clock (counter clock).
Bit 3 Reserved
Bits 2–0 CLKSRC[2:0]
These bits select the clock source of T16B Ch.n.
0x0
T16B_nCLK.
CLKDIV[3:0] bits
IOSC
0xf 1/32,768
0xe 1/16,384
0xd 1/8,192
0xc 1/4,096
0xb 1/2,048
0xa 1/1,024
0x9 1/512
0x8 1/256
0x7 1/128
0x6 1/64
0x5 1/32
0x4 1/16
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
(Note) The oscillator circuits/external inputs that are not supported in this IC cannot be selected as the clock source.

T16B Ch.n Counter Control Register

Register name Bit
T16B_nCTL 15–9 –
8
7–6 –
5–4 CNTMD[1:0]
3
2
1
0
Bits 15–9 Reserved
Bit 8 MAXBSY
This bit indicates whether data can be written to the T16B_nMC register or not.
1 (R): Busy status (cannot be written)
0 (R): Idle (can be written)
While this bit is 1, the T16B_nMC register is loading the MAX value. Data writing is prohibited dur-
ing this period.
Bits 7–6 Reserved
Bits 5–4 CNTMD[1:0]
These bits select the counter up/down mode. The count mode is configured with this selection and the
T16B_nCTL.ONEST bit setting (see Table 17.7.2).
Bit 3 ONEST
This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection
and the T16B_nCTL.CNTMD[1:0] bit settings (see Table 17.7.2).
17-24
Table 17.7.1 Clock Source and Division Ratio Settings
0x1 0x2
OSC1 OSC3
1/1 1/32,768
1/16,384
1/8,192
1/4,096
1/2,048
1/1,024
1/512
1/256 1/256
1/128 1/128
1/64 1/64
1/32 1/32
1/16 1/16
1/8 1/8
1/4 1/4
1/2 1/2
1/1 1/1
Bit name Initial
0x00
MAXBSY 0
0x0
0x0
ONEST 0
RUN 0
PRESET 0
MODEN 0
Seiko Epson Corporation
T16B_nCLK.CLKSRC[2:0] bits
0x3 0x4
EXOSC EXCLn0
1/1 1/1
Reset R/W
– R –
H0 R
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
0x5 0x6
EXCLn0 EXCLn1
EXCLn1 inverted inverted
input input
1/1 1/1
Remarks
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
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