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15 Quad Synchronous Serial Interface (QSPI)
Register access master mode
QSPI_nMOD register
CPOL bit
1
0
Slave mode
QSPI_nMOD register
CPOL bit
1
0
Memory mapped access mode
QSPI_nMOD register
#QSPISSn
CPOL bit
CPHA bit
1
1
QSPICLKn
0
0
QSDIOn[3:0]
QSPI_nINTF.MMABSY
Figure 15.6.1 QSPI_nINTF.BSY, QSPI_nINTF.MMABSY, and QSPI_nINTF.TENDIF Bit Set Timings
(when QSPI_nMOD.CHDL[3:0] bits = QSPI_nMOD.CHLN[3:0] bits = 0x3)
15.7 DMA Transfer Requests
The QSPI has a function to generate DMA transfer requests from the causes shown in Table 15.7.1.
Cause to request
DMA transfer request flag
DMA transfer
Receive buffer full Receive buffer full flag
(QSPI_nINTF.RBFIF)
Transmit buffer
Transmit buffer empty flag
empty
(QSPI_nINTF.TBEIF)
Memory mapped
Memory mapped access
access FIFO data
FIFO data ready flag
ready
(internal signal)
15-28
CPHA bit
1
QSPICLKn
0
QSDIOn[3:0]
QSPI_nINTF.BSY
QSPI_nINTF.TENDIF
#QSPISSn
QSPI_nINTF.BSY
CPHA bit
QSPICLKn
1
QSDIOn[3:0]
QSPICLKn
0
QSDIOn[3:0]
QSPI_nINTF.TENDIF
#QSPISSn
inactive period
(TCSH)
(high-order 8/16 bits)
1 (W) → QSPI_nMMACFG2.MMAEN
Table 15.7.1 DMA Transfer Request Causes of QSPI
When data of the specified bit length is re-
ceived and the received data is transferred from
the shift register to the received data buffer
When transmit data written to the transmit data
buffer is transferred to the shift register
When a 32-bit data is prefetched into the FIFO
in memory mapped access mode
Seiko Epson Corporation
1
2
Writing data to the QSPI_nTXD register
1
2
Writing data to the QSPI_nTXD register
Address cycle
Address cycle
(low-order 16 bits)
Set condition
3
4
3
4
Dummy cycle
0 (W) → QSPI_nMMACFG2.MMAEN
Clear condition
Reading of the QSPI_
nRXD register
Writing to the QSPI_
nTXD register
When the FIFO read
level is cleared to 0
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
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