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15 Quad Synchronous Serial Interface (QSPI)
Table 15.8.5 Settings of Data Line Drive Length during Dummy Cycle
QSPI_nMMACFG2.DUMDL[3:0] bits
These bits must be set to a value smaller than or equal to the QSPI_nMMACFG2.DUMLN[3:0] bit
setting.
Bits 11–8 DUMLN[3:0]
These bits set the dummy cycle length in a number of clocks when accessing the external Flash mem-
ory in the memory mapped access mode.
QSPI_nMMACFG2.DUMLN[3:0] bits
Bits 7–6
DATTMOD[1:0]
These bits select the transfer mode for the data cycle when accessing the external Flash memory in the
memory mapped access mode.
Table 15.8.7 Transfer Mode for Data, Dummy, and Address Cycles
QSPI_nMMACFG2.DATTMOD[1:0] bits
QSPI_nMMACFG2.DUMTMOD[1:0] bits
QSPI_nMMACFG2.ADRTMOD[1:0] bits
0x3
0x2
0x1
0x0
15-36
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Table 15.8.6 Dummy Cycle Length Settings
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Reserved
Quad transfer mode
The QSDIOn[3:0] pins are used.
Dual transfer mode
The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used.
Single transfer mode
The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used.
Seiko Epson Corporation
Data line drive length
16 clocks
15 clocks
14 clocks
13 clocks
12 clocks
11 clocks
10 clocks
9 clocks
8 clocks
7 clocks
6 clocks
5 clocks
4 clocks
3 clocks
2 clocks
1 clock
Dummy cycle length
16 clocks
15 clocks
14 clocks
13 clocks
12 clocks
11 clocks
10 clocks
9 clocks
8 clocks
7 clocks
6 clocks
5 clocks
4 clocks
3 clocks
2 clocks
Setting prohibited
Transfer mode
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
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