Data Format - Epson S1C31D50 Technical Manual

15 Quad Synchronous Serial Interface (QSPI)

15.4 Data Format

The QSPI data length can be selected from 2 to 16 clocks by setting the QSPI_nMOD.CHLN[3:0] bits. The input/
output permutation is configurable to MSB first or LSB first using the QSPI_nMOD.LSBFST bit. Figures 15.4.1 to
15.4.3 show data format examples in different transfer modes (QSPI_nMOD.TMOD[1:0]) when the QSPI_nMOD.
CPOL bit = 0 and the QSPI_nMOD.CPHA bit = 0.
Cycle No.
QSPI_nMOD. QSPICLKn
LSBFST bit
QSDIOn0
0
QSDIOn1
QSDIOn0
1
QSDIOn1
Figure 15.4.1 Data Format Selection for Single Transfer Mode Using the QSPI_nMOD.LSBFST Bit
(QSPI_nMOD.TMOD[1:0] bits = 0x0, QSPI_nMOD.CHLN[3:0] bits = 0x7, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0)
Cycle No.
QSPI_nMOD. QSPICLKn
LSBFST bit
QSDIOn1
QSDIOn0
0
QSDIOn1
QSDIOn0
QSDIOn1
QSDIOn0
1
QSDIOn1
QSDIOn0
Writing Dw[15:0] to the QSPI_nTXD register
Figure 15.4.2 Data Format Selection for Dual Transfer Mode Using the QSPI_nMOD.LSBFST Bit
(QSPI_nMOD.TMOD[1:0] bits = 0x1, QSPI_nMOD.CHLN[3:0] bits = 0x7, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0)
15-8
1 2
Dw7 Dw6
Dr7 Dr6
Dw0 Dw1
Dr0 Dr1
Writing Dw[7:0] to the QSPI_nTXD register
1 2
Dw15 Dw13
Dw14 Dw12
Dr15 Dr13
Dr14 Dr12
Dw0 Dw2
Dw1 Dw3
Dr0 Dr2
Dr1 Dr3
Seiko Epson Corporation
3 4 5
Dw5 Dw4 Dw3
Dr5 Dr4 Dr3
Dw2 Dw3 Dw4
Dr2 Dr3 Dr4
Loading Dr[7:0] to the QSPI_nRXD register
3 4 5
Dw11 Dw9 Dw7
Dw10 Dw8 Dw6
Dr11 Dr9 Dr7
Dr10 Dr8 Dr6
Dw4 Dw6 Dw8
Dw5 Dw7 Dw9
Dr4 Dr6 Dr8
Dr5 Dr7 Dr9
Loading Dr[15:0] to the QSPI_nRXD register
6 7 8
Dw2 Dw1 Dw0
Dr2 Dr1 Dr0
Dw5 Dw6 Dw7
Dr5 Dr6 Dr7
6 7 8
Dw5 Dw3 Dw1
Dw4 Dw2 Dw0
Dr5 Dr3 Dr1
Dr4 Dr2 Dr0
Dw10 Dw12 Dw14
Dw11 Dw13 Dw15
Dr10 Dr12 Dr14
Dr11 Dr13 Dr15
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)