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14 SYNCHRONOUS SERIAL INTERFACE (SPIA)
14.6 Interrupts
SPIA has a function to generate the interrupts shown in Table 14.6.1.
Interrupt
End of transmission
SPIA_nINTF.TENDIF When the SPIA_nINTF.TBEIF bit = 1 after data
Receive buffer full
SPIA_nINTF.RBFIF
Transmit buffer empty SPIA_nINTF.TBEIF
Overrun error
SPIA_nINTF.OEIF
SPIA provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU
core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more
information on interrupt control, refer to the "Interrupt" chapter.
The SPIA_nINTF register also contains the BSY bit that indicates the SPIA operating status.
Figure 14.6.1 shows the SPIA_nINTF.BSY and SPIA_nINTF.TENDIF bit set timings.
Master mode
SPIA_nMOD register
CPOL bit
CPHA bit
1
0
SPIA_nINTF.BSY
SPIA_nINTF.TENDIF
Slave mode
SPIA_nINTF.BSY
SPIA_nMOD register
CPOL bit
CPHA bit
1
1
0
0
SPIA_nINTF.TENDIF
Figure 14.6.1 SPIA_nINTF.BSY and SPIA_nINTF.TENDIF Bit Set Timings (when SPIA_nMOD.CHLN[3:0] bits = 0x7)
14-12
Table 14.6.1 SPIA Interrupt Function
Interrupt flag
of the specified bit length (defined by the SPIA_
nMOD.CHLN[3:0] bits) has been sent
When data of the specified bit length is received
and the received data is transferred from the shift
register to the received data buffer
When transmit data written to the transmit data
buffer is transferred to the shift register
When the receive data buffer is full (when the re-
ceived data has not been read) at the point that
receiving data to the shift register has completed
1
SPICLKn
0
SDOn
Writing data to the SPIA_nTXD register
#SPISSn
SPICLKn
SDOn
SPICLKn
SDOn
Writing data to the SPIA_nTXD register
Seiko Epson Corporation
Set condition
1
2
3
1
2
3
Clear condition
Writing 1
Reading the SPIA_
nRXD register
Writing to the SPIA_
nTXD register
Writing 1
7
8
7
8
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
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