Epson S1C31D50 Technical Manual page 208

HCLK
HSEL
HADDR
HTRANS
HSIZE
HREADY
HRDATA
QSPI_nMOD register #QSPISSn
CPOL bit CPHA bit
1 1
QSPICLKn
0 0
QSDIOn[3:0]
HCLK
HSEL
HADDR
HTRANS
HSIZE
HREADY
HRDATA
QSPI_nMOD register #QSPISSn
CPOL bit CPHA bit
1 1
QSPICLKn
0 0
QSDIOn[3:0]
Figure 15.5.6.6 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Non-Sequential Read
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
n
2
0/1
#QSPISSn
inactive
period
(TCSH)
Address cycle
(low-order 16 bits)
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
Address cycle
(high-order 8/16 bits)
Dummy cycle
Address cycle
(low-order 16 bits)
n
Data cycle
15-23