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13.3.2 Clock Supply in SLEEP Mode
When using the UART3 during SLEEP mode, the UART3 operating clock CLK_UART3_n must be configured so
that it will keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_UART3_n clock source.
13.3.3 Clock Supply During Debugging
The CLK_UART3_n supply during debugging should be controlled using the UART3_nCLK.DBRUN bit.
The CLK_UART3_n supply to the UART3 Ch.n is suspended when the CPU enters debug state if the UART3_
nCLK.DBRUN bit = 0. After the CPU returns to normal mode, the CLK_UART3_n supply resumes. Although the
UART3 Ch.n stops operating when the CLK_UART3_n supply is suspended, the output pin and registers retain the
status before the debug state was entered. If the UART3_nCLK.DBRUN bit = 1, the CLK_UART3_n supply is not
suspended and the UART3 Ch.n will keep operating in a debug state.
13.3.4 Baud Rate Generator
The UART3 includes a baud rate generator to generate the transfer (sampling) clock. The transfer rate is determined
by the UART3_nMOD.BRDIV, UART3_nBR.BRT[7:0], and UART3_nBR.FMD[3:0] bit settings. Use the follow-
ing equations to calculate the setting values for obtaining the desired transfer rate.
CLK_UART3
bps = —————————
BRT + 1
———— + FMD
BRDIV
Where
bps:
Transfer rate [bit/s]
CLK_UART3: UART3 operating clock frequency [Hz]
Baud rate division ratio (1/16 or 1/4) * Selected by the UART3_nMOD.BRDIV bit
BRDIV:
BRT:
UART3_nBR.BRT[7:0] setting value (0 to 255)
FMD:
UART3_nBR.FMD[3:0] setting value (0 to 15)
For the transfer rate range configurable in the UART3, refer to "UART Characteristics, Transfer baud rates U
and U
" in the "Electrical Characteristics" chapter.
BRT2
13.4 Data Format
The UART3 allows setting of the data length, stop bit length, and parity function. The start bit length is fixed at one
bit.
Data length
With the UART3_nMOD.CHLN bit, the data length can be set to seven bits (UART3_nMOD.CHLN bit = 0) or
eight bits (UART3_nMOD.CHLN bit = 1).
Stop bit length
With the UART3_nMOD.STPB bit, the stop bit length can be set to one bit (UART3_nMOD.STPB bit = 0) or
two bits (UART3_nMOD.STPB bit = 1).
Parity function
The parity function is configured using the UART3_nMOD.PREN and UART3_nMOD.PRMD bits.
UART3_nMOD.PREN bit UART3_nMOD.PRMD bit
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
BRT = BRDIV ×
Table 13.4.1 Parity Function Setting
1
1
1
0
0
*
Seiko Epson Corporation
(
)
CLK_UART3
—————— - FMD
- 1
bps
Parity function
Odd parity
Even parity
Non parity
13 UART (UART3)
(Eq. 13.1)
BRT1
13-3
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