Interrupt; Dma Transfer Requests; Control Registers; T16B Ch.n Clock Control Register - Epson S1C31D50 Technical Manual

17.5 Interrupt

Each T16B channel has a function to generate the interrupt shown in Table 17.5.1.
Interrupt Interrupt flag
Capture T16B_nINTF.CAPOWmIF When the T16B_nINTF.CMPCAPmIF bit =1 and the T16B_
overwrite
Compare/ T16B_nINTF.CMPCAPmIF When the counter value becomes equal to the compare
capture
Counter MAX T16B_nINTF.CNTMAXIF
Counter zero T16B_nINTF.CNTZEROIF When the counter reaches 0x0000
T16B provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU
core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more
information on interrupt control, refer to the "Interrupt" chapter.

17.6 DMA Transfer Requests

The T16B has a function to generate DMA transfer requests from the causes shown in Table 17.6.1.
Cause to request
DMA transfer request flag
DMA transfer
Compare/ Compare/capture flag
capture (T16B_nINTF.CMPCAPmIF)
Counter MAX/ Counter MAX flag
zero (T16B_nINTF.CNTMAXIF)
Counter zero flag
(T16B_nINTF.CNTZEROIF)
The T16B provides DMA transfer request enable bits corresponding to each DMA transfer request flag shown
above for the number of DMA channels. A DMA transfer request is sent to the pertinent channel of the DMA con-
troller only when the DMA transfer request flag, of which DMA transfer has been enabled by the DMA transfer
request enable bit, is set. The DMA transfer request flag also serves as an interrupt flag, therefore, both the DMA
transfer request and the interrupt cannot be enabled at the same time. After a DMA transfer has completed, disable
the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the
DMA control, refer to the "DMA Controller" chapter.

17.7 Control Registers

T16B Ch.n Clock Control Register

Register name Bit
T16B_nCLK 15–9 –
8
7–4 CLKDIV[3:0]
3
2–0 CLKSRC[2:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the T16B Ch.n operating clock is supplied during debugging or not.
1 (R/W): Clock supplied during debugging
0 (R/W): No clock supplied during debugging
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Table 17.5.1 T16B Interrupt Function
n CCRm register is overwritten with new captured data in
capture mode
buffer value in comparator mode
When the counter value is loaded to the T16B_nCCRm reg-
ister by a capture trigger input in capture mode
When the counter reaches the MAX value
Table 17.6.1 DMA Transfer Request Causes of T16B
When the counter value becomes equal to the com-
pare buffer value in comparator mode
When the counter value is loaded to the T16B_nCCRm
register by a capture trigger input in capture mode
When the counter reaches the MAX value in up or up/
down count mode
When the counter reaches 0x0000 in down count
mode
Bit name Initial
0x00
DBRUN 0
0x0
– 0
0x0
Seiko Epson Corporation
17 16-BIT PWM TIMERS (T16B)
Set condition
Set condition
Reset R/W
– R –
H0 R/W
H0 R/W
– R
H0 R/W
Clear condition
Writing 1
Writing 1
Writing 1
Writing 1
Clear condition
When the
DMA transfer
request is ac-
cepted
When the
DMA transfer
request is ac-
cepted
Remarks
17-23