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21 HW Processor (HWP) and Sound Output
7. Configure the T16B Ch.0 operating clock. (Refer to Section 21.3, "Clock Settings.")
- Set the T16B_0CLK.CLKSRC[2:0] bits to 0x02.
- Set the T16B_0CLK.CLKDIV[3:0] bits to 0x0.
- Set the T16B_0CLK.DBRUN bit to 1.
8. Write 1 to the 16B_0CTL.MODEN bit.
9. Set the T16B_0CCCTLm registers as follows:
- T16B_0CCCTL0 register = 0x101c
- T16B_0CCCTL1 register = 0x101c
- T16B_0CCCTL2 register = 0x8b01
- T16B_0CCCTL3 register = 0x8b01
10. Set the T16B_0MC.MC[15:0] bits to 0x03ff.
11. Set the T16B_0CCRm registers as follows:
- T16B_0CCR0 register = 0x0200
- T16B_0CCR1 register = 0x0200
12. Disable T16B Ch.0 interrupts to occur.
- Set the T16B_0INTE register to 0x0000.
- Write 0x03ff to the T16B_0INTF register.
13. Write 1 to the T16B_0CTL.PRESET bit.
Initializing HWP (sound play function)
14. Set the HWPCTL.HWPEN bit to 0.
15. Set the following HWP internal register bits (sound play function register bits):
- Set the FUNCTION.ID[7:0] bits to 0x02.
- INTMASK.TO_MUTE bit
- INTMASK.TO_PAUSE bit
- INTMASK.TO_PLAY bit
- INTMASK.TO_IDLE bit
- ROMADDR.ADDRESS[31:0] bits
- ROMSIZE.SIZE[31:0] bits
- KEYCODE.KEYCODE[31:0] bits
16. Perform the following settings when using the HWP interrupt:
- Set the HWP interrupt level (refer to the "Cortex®-M0+ Technical Reference Manual").
- Write 0 to all the interrupt flags in the HWPINTF register. (Clear interrupt flags)
Note: Be aware that the write value to clear flags is different from other peripheral circuits.
- Set the HWPINTE.HWPIE bit to 1. (Enable interrupts)
Starting HWP operation (sound play function)
17. Write 1 to the T16B_0CTL.RUN bit.
18. Set the SDACMOD.PWMOUTEN bit to 1.
19. Enable the external amplifier using a general-purpose output port (if necessary).
* Set a wait time according to the amplifier specifications after being enabled.
20. Set the HWPCTL.HWPEN bit to 1.
21. Wait until the HWPINTF.HWP0IF bit is set to 1 and the STATE_n.STATE[15:0] bits are set to 0x0001
(sp_state_idle = sound play function idle state).
Initialize the SDAC, T16B Ch.0, and HWP in this order again if the HWPINTF.HWP1IF bit = 1.
Sound play state transition
Figure 21.4.1.1 shows the sound play state transition diagram.
21-6
(Clock source = OSC3)
(Clock division ratio = 1/1)
(Enable clock supply in DEBUG mode)
(Enable T16B Ch.0)
(Configure comparator circuit 0)
(Configure comparator circuit 1)
(Configure capture circuit 2)
(Configure capture circuit 3)
(Set MAX value)
(Set compare data 0)
(Set compare data 1)
(Disable all T16B Ch.0 interrupts)
(Clear all T16B Ch.0 interrupt flags)
(Reset counter)
(Disable HWP)
(Select sound play function)
(Set mute interrupt mask)
(Set pause interrupt mask)
(Set playback start interrupt mask)
(Set idle state interrupt mask)
(Set sound ROM data start address)
(Set sound ROM data size)
(Set key code)
(Start T16B Ch.0)
(Enable sound output)
(Enable HWP)
Seiko Epson Corporation
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
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