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22 ELECTRICAL CHARACTERISTICS
t
f
t
r
SDAn
t
HD:DAT
t
f
SCLn
S
t
HD:STA
1/f
SCL
1st clock cycle
22.13 12-bit A/D Converter (ADC12A) Characteristics
Unless otherwise specified: V
DD
ADC12A_nTRG.SMPCLK[2:0] bits = 0x3 (7cycles)
Item
VREFAn voltage range
V
REFA
A/D conversion clock
f
CLK_ADC12A
frequency
Sampling rate
f
*1
SMP
Integral nonlinearity
INL
*2
Differential nonlinearity
DNL
Zero-scale error
ZSE
Full-scale error
FSE
Analog input resistance
R
ADIN
Analog input capacitance
C
ADIN
A/D converter circuit
I
ADC
current
*1 The Max. value is the value when the A/D conversion clock frequency f
*2 Integral nonlinearity is measured at the end point line.
*3 The error will be increased according to the potential difference between V
A/D converter current consumption-power supply voltage characteristic
V
= V
, ADIN = V
/2, f
DD
REFA
REFA
SMP
1,100
ADC12A_nCFG.VRANGE[1:0] bits =
1,000
900
800
700
600
500
400
300
200
100
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V
DD
22-14
t
SU:DAT
t
t
r
HIGH
t
LOW
= 2.5 to 5.5 V, VREFAn = 1.8 to 5.5 V, V
Symbol
Condition
V
= VREFAn
*3
DD
V
= VREFAn
*3
DD
V
= VREFAn
*3
DD
V
= VREFAn
*3
DD
ADC12A_nCFG.VRANGE[1:0] bits = 0x3,
V
= V
, ADIN = V
DD
REFA
Ta = 25°C
ADC12A_nCFG.VRANGE[1:0] bits = 0x2,
V
= V
, ADIN = V
DD
REFA
Ta = 25°C
ADC12A_nCFG.VRANGE[1:0] bits = 0x1,
V
= V
, ADIN = V
DD
REFA
Ta = 25°C
= 100 ksps, Ta = 25°C, Typ. value
0x3
0x2
0x1
= V
[V]
REFA
Seiko Epson Corporation
t
SU:STA
t
HD:STA
Sr
9th clock cycle
= 0 V, Ta = -40 to 85°C,
SS
V
3.6 V
/2, f
= 100 ksps,
REFA
SMP
4.8 V
/2, f
= 100 ksps,
REFA
SMP
5.5 V
/2, f
= 100 ksps,
REFA
SMP
= 2,000 kHz.
CLK_ADC12A
and VREFAn.
DD
t
BUF
t
SU:STO
P
S
S: START condition
Sr: Repeated START condition
P: STOP condition
Min.
Typ.
Max.
DD
1.8
–
V
DD
16
–
2,200
–
–
100
–
–
±3
–
–
±3
–
–
±5
–
–
±5
–
–
4
–
–
30
–
400
700
–
230
470
–
210
390
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Unit
V
kHz
ksps
LSB
LSB
LSB
LSB
kW
pF
µA
µA
µA
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