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4 MEMORY AND BUS
Peripheral circuit
16-bit timer (T16) Ch.2
Quad synchronous serial
interface (QSPI) Ch.0
I
C (I2C) Ch.1
2
I
C (I2C) Ch.2
2
IR remote controller (REMC3) 0x0020 0720 REMC3CLK
16-bit timer (T16) Ch.7
12-bit A/D converter
(ADC12A) Ch.0
4-8
Address
0x0020 0688 T16_2TC
0x0020 068a T16_2INTF
0x0020 068c T16_2INTE
0x0020 0690 QSPI_0MOD
0x0020 0692 QSPI_0CTL
0x0020 0694 QSPI_0TXD
0x0020 0696 QSPI_0RXD
0x0020 0698 QSPI_0INTF
0x0020 069a QSPI_0INTE
0x0020 069c QSPI_0TBEDMAEN QSPI Ch.0 Transmit Buffer Empty DMA Request Enable Register
0x0020 069e QSPI_0RBFDMAEN QSPI Ch.0 Receive Buffer Full DMA Request Enable Register
0x0020 06a0 QSPI_0FRLDMAEN QSPI Ch.0 FIFO Data Ready DMA Request Enable Register
0x0020 06a2 QSPI_0MMACFG1
0x0020 06a4 QSPI_0RMADRH
0x0020 06a6 QSPI_0MMACFG2
0x0020 06a8 QSPI_0nMB
0x0020 06c0 I2C_1CLK
0x0020 06c2 I2C_1MOD
0x0020 06c4 I2C_1BR
0x0020 06c8 I2C_1OADR
0x0020 06ca I2C_1CTL
0x0020 06cc I2C_1TXD
0x0020 06ce I2C_1RXD
0x0020 06d0 I2C_1INTF
0x0020 06d2 I2C_1INTE
0x0020 06d4 I2C_1TBEDMAEN
0x0020 06d6 I2C_1RBFDMAEN
0x0020 06e0 I2C_2CLK
0x0020 06e2 I2C_2MOD
0x0020 06e4 I2C_2BR
0x0020 06e8 I2C_2OADR
0x0020 06ea I2C_2CTL
0x0020 06ec I2C_2TXD
0x0020 06ee I2C_2RXD
0x0020 06f0 I2C_2INTF
0x0020 06f2 I2C_2INTE
0x0020 06f4 I2C_2TBEDMAEN
0x0020 06f6 I2C_2RBFDMAEN
0x0020 0722 REMC3DBCTL
0x0020 0724 REMC3DBCNT
0x0020 0726 REMC3APLEN
0x0020 0728 REMC3DBLEN
0x0020 072a REMC3INTF
0x0020 072c REMC3INTE
0x0020 0730 REMC3CARR
0x0020 0732 REMC3CCTL
0x0020 0780 T16_7CLK
0x0020 0782 T16_7MOD
0x0020 0784 T16_7CTL
0x0020 0786 T16_7TR
0x0020 0788 T16_7TC
0x0020 078a T16_7INTF
0x0020 078c T16_7INTE
0x0020 07a2 ADC12A_0CTL
0x0020 07a4 ADC12A_0TRG
0x0020 07a6 ADC12A_0CFG
0x0020 07a8 ADC12A_0INTF
0x0020 07aa ADC12A_0INTE
0x0020 07ac ADC12A_0DMAEN0 ADC12A Ch.0 DMA Request Enable Register 0
0x0020 07ae ADC12A_0DMAEN1 ADC12A Ch.0 DMA Request Enable Register 1
0x0020 07b0 ADC12A_0DMAEN2 ADC12A Ch.0 DMA Request Enable Register 2
0x0020 07b2 ADC12A_0DMAEN3 ADC12A Ch.0 DMA Request Enable Register 3
0x0020 07b4 ADC12A_0DMAEN4 ADC12A Ch.0 DMA Request Enable Register 4
Seiko Epson Corporation
Register name
T16 Ch.2 Counter Data Register
T16 Ch.2 Interrupt Flag Register
T16 Ch.2 Interrupt Enable Register
QSPI Ch.0 Mode Register
QSPI Ch.0 Control Register
QSPI Ch.0 Transmit Data Register
QSPI Ch.0 Receive Data Register
QSPI Ch.0 Interrupt Flag Register
QSPI Ch.0 Interrupt Enable Register
QSPI Ch.0 Memory Mapped Access Configuration Register 1
QSPI Ch.0 Remapping Start Address High Register
QSPI Ch.0 Memory Mapped Access Configuration Register 2
QSPI Ch.0 Mode Byte Register
I2C Ch.1 Clock Control Register
I2C Ch.1 Mode Register
I2C Ch.1 Baud-Rate Register
I2C Ch.1 Own Address Register
I2C Ch.1 Control Register
I2C Ch.1 Transmit Data Register
I2C Ch.1 Receive Data Register
I2C Ch.1 Status and Interrupt Flag Register
I2C Ch.1 Interrupt Enable Register
I2C Ch.1 Transmit Buffer Empty DMA Request Enable Register
I2C Ch.1 Receive Buffer Full DMA Request Enable Register
I2C Ch.2 Clock Control Register
I2C Ch.2 Mode Register
I2C Ch.2 Baud-Rate Register
I2C Ch.2 Own Address Register
I2C Ch.2 Control Register
I2C Ch.2 Transmit Data Register
I2C Ch.2 Receive Data Register
I2C Ch.2 Status and Interrupt Flag Register
I2C Ch.2 Interrupt Enable Register
I2C Ch.2 Transmit Buffer Empty DMA Request Enable Register
I2C Ch.2 Receive Buffer Full DMA Request Enable Register
REMC3 Clock Control Register
REMC3 Data Bit Counter Control Register
REMC3 Data Bit Counter Register
REMC3 Data Bit Active Pulse Length Register
REMC3 Data Bit Length Register
REMC3 Status and Interrupt Flag Register
REMC3 Interrupt Enable Register
REMC3 Carrier Waveform Register
REMC3 Carrier Modulation Control Register
T16 Ch.7 Clock Control Register
T16 Ch.7 Mode Register
T16 Ch.7 Control Register
T16 Ch.7 Reload Data Register
T16 Ch.7 Counter Data Register
T16 Ch.7 Interrupt Flag Register
T16 Ch.7 Interrupt Enable Register
ADC12A Ch.0 Control Register
ADC12A Ch.0 Trigger/Analog Input Select Register
ADC12A Ch.0 Configuration Register
ADC12A Ch.0 Interrupt Flag Register
ADC12A Ch.0 Interrupt Enable Register
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
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