Nmi - Epson S1C31D50 Technical Manual

Cmos 32-bit single chip

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For specific information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respective pe-

ripheral circuit descriptions.

Note: To prevent occurrence of unnecessary interrupts, the corresponding interrupt flag should be

cleared before setting the interrupt enable bit to 1 (interrupt enabled) and before terminating the

interrupt handler routine.

5.4 NMI

The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes prece-

dence over other interrupts and is unconditionally accepted by the CPU.

For detailed information on generating NMI, refer to the "Watchdog Timer" chapter.

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S1C31D50/D51 TECHNICAL MANUAL