Epson S1C31D50 Technical Manual page 408

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Address Register name
0x0020 T16_6INTF
066a (T16 Ch.6 Interrupt
Flag Register)
0x0020 T16_6INTE
066c
(T16 Ch.6 Interrupt
Enable Register)
0x0020 0670–0x0020 067e
Address Register name
0x0020 SPIA_1MOD
0670
(SPIA Ch.1 Mode
Register)
0x0020 SPIA_1CTL
0672
(SPIA Ch.1 Control
Register)
0x0020 SPIA_1TXD
0674
(SPIA Ch.1 Transmit
Data Register)
0x0020 SPIA_1RXD
0676 (SPIA Ch.1 Receive
Data Register)
0x0020 SPIA_1INTF
0678 (SPIA Ch.1 Interrupt
Flag Register)
0x0020 SPIA_1INTE
067a
(SPIA Ch.1 Interrupt
Enable Register)
0x0020 SPIA_1TBEDMAEN
067c (SPIA Ch.1 Transmit
Buffer Empty DMA
Request Enable
Register)
0x0020 SPIA_1RBFDMAEN
067e
(SPIA Ch.1 Receive
Buffer Full DMA
Request Enable
Register)
AP-A-44
Bit Bit name
15–8 –
7–1 –
0 UFIF
15–8 –
7–1 –
0 UFIE
Bit Bit name
15–12 –
11–8 CHLN[3:0]
7–6 –
5 PUEN
4 NOCLKDIV
3 LSBFST
2 CPHA
1 CPOL
0 MST
15–8 –
7–2 –
1 SFTRST
0 MODEN
15–0 TXD[15:0]
15–0 RXD[15:0]
15–8 –
7 BSY
6–4 –
3 OEIF
2 TENDIF
1 RBFIF
0 TBEIF
15–8 –
7–4 –
3 OEIE
2 TENDIE
1 RBFIE
0 TBEIE
15–8 –
7–4 –
3–0 TBEDMAEN[3:0]
15–8 –
7–4 –
3–0 RBFDMAEN[3:0]
Seiko Epson Corporation
Initial Reset R/W
0x00 – R
0x00 – R
0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
Synchronous Serial Interface (SPIA) Ch.1
Initial Reset R/W
0x0 – R
0x7 H0 R/W
0x0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
0 H0 R/W
0x0000 H0 R/W
0x0000 H0 R
0x00 – R
0 H0 R
0x0 – R
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R
1 H0/S0 R
0x00 – R
0x0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
S1C31D50/D51 TECHNICAL MANUAL
Remarks
–
Cleared by writing 1.
–
Remarks
–
–
–
–
–
Cleared by writing 1.
Cleared by reading the
SPIA_1RXD register.
Cleared by writing to the
SPIA_1TXD register.
–
–
–
(Rev. 2.00)