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S1C31D50/D51 lineup
Current consumption (Typ. value)
SLEEP mode
*1
HALT mode
*2
RUN mode
Shipping form
Package
*3
*1 SLEEP mode refers to deep sleep mode in the Cortex
*2 HALT mode refers to sleep mode in the Cortex
*3 Shown in parentheses are JEITA package names.
1.2 Block Diagram
SWCLK
CPU core, interrpt controller, and debuger
(Cortex
SWD
System clock
Clock generator
(CLG)
IOSC
FOUT
oscillator
OSC1
OSC1
oscillator
OSC2
OSC3
OSC3
oscillator
OSC4
EXOSC
EXOSC
input circuit
System reset controller
(SRC)
Power-on reset
(POR)
#RESET
Brown-out reset
(BOR)
V
DD
Power generator
V
SS
(PWGA)
V
D1
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
48-pin package
0.46 µA
IOSC = OFF, OSC1 = OFF, OSC3 = OFF
0.95 µA
IOSC = OFF, OSC1 = 32.768 kHz (crystal oscillator), OSC3 = OFF, RTCA = ON
1.8 µA
IOSC = OFF, OSC1 = 32.768 kHz (crystal oscillator), OSC3 = OFF
250 µA/MHz
V
voltage mode = mode0, CPU = IOSC
D1
155 µA/MHz
V
voltage mode = mode1, CPU = IOSC
D1
TQFP12-48PIN
(P-TQFP048-0707-0.50,
7 × 7 mm, t = 1.2 mm,
0.5 mm pitch)
-M0+ processor.
®
-M0+ processor.
®
®
-M0+)
16-bit peripheral bus
DMA request signal
Interrupt signal
I/O port 01
(PPORT)
I/O port 23
(PPORT)
I/O port others
(PPORT)
Watchdog timer
(WDT2)
Real-time clock
(RTCA)
Supply voltage
detector
(SVD3)
1 Ch.
16-bit timer
(T16)
8 Ch.
16-bit PWM timer
(T16B)
2 Ch.
* The pin configuration depends on the package. For detailed information, refer to Section 1.3, "Pins."
Figure 1.2.1 S1C31D50/D51 Block Diagram
Seiko Epson Corporation
64-pin package
80-pin package
QFP13-64PIN
TQFP14-80PIN
(P-LQFP064-1010-0.50,
(P-TQFP080-1212-0.50,
10 × 10 mm, t = 1.7 mm,
12 × 12 mm, t = 1.2 mm,
0.5 mm pitch)
0.5 mm pitch)
Cache controller
Cache RAM
512 bytes
DMA controller
P0*
P1*
P2*
P3*
P4*
P5*
P6*
P7*
P8*
P9*
PA*
PD*
RTC1S
EXSVD0–1
TOUT00–03
TOUT10–13
CAP00–03
CAP10–13
EXCL00–03
EXCL10–13
1 OVERVIEW
100-pin package
QFP15-100PIN
(P-LQFP100-1414-0.50,
14 × 14 mm, t = 1.7 mm,
0.5 mm pitch)
MTB
RAM
8K bytes (D50)
10K bytes (D51)
Flash memory
V
PP
192K bytes
HW processor
(HWP)
RAM
14K bytes (D50)
12K bytes (D51)
Quad
V
DDQSPI
synchronous
QSDIO00–03
serial interface
QSPICLK0
(QSPI)
#QSPISS0
1 Ch.
UART
USIN0–2
(UART3)
USOUT0–2
3 Ch.
Synchronous
SDI0–2
serial interface
SDO0–2
(SPIA)
SPICLK0–2
3 Ch.
#SPISS0–2
2
I
C
SDA0–2
(I2C)
SCL0–2
3 Ch.
IR remote
controller
REMO
(REMC3)
CLPLS
1 Ch.
RFIN0
R/F converter
REF0
(RFC)
SENA0
1 Ch.
SENB0
RFCLKO0
12-bit A/D
#ADTRG0
converter
ADIN0 *
(ADC12A)
VREFA0
1 Ch.
Sound DAC
SDACOUT_P
(SDAC)
SDACOUT_N
1 Ch.
1-3
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