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1 OVERVIEW
1.2 Block Diagram
CPU core, interrpt controller, and debuger
SWCLK
(Cortex
SWD
System clock
Clock generator
(CLG)
IOSC
FOUT
oscillator
OSC1
OSC1 *
oscillator
OSC2 *
OSC3
OSC3
oscillator
OSC4
EXOSC
EXOSC
input circuit
System reset controller
(SRC)
Power-on reset
(POR)
#RESET
Brown-out reset
(BOR)
V
DD
Power generator
V
SS
(PWGA)
V
D1
1-4
®
-M0+)
16-bit peripheral bus
DMA request signal
Interrupt signal
I/O port 01
(PPORT)
I/O port 23
(PPORT)
I/O port others
(PPORT)
Watchdog timer
(WDT2)
Real-time clock
(RTCA)
Supply voltage
detector
(SVD3)
1 Ch.
16-bit timer
(T16)
8 Ch.
16-bit PWM timer
(T16B)
2 Ch.
UART
(UART3)
3 Ch.
* The pin configuration depends on the package. For detailed information, refer to Section 1.3, "Pins."
Figure 1.2.1 S1C31D41 Block Diagram
Seiko Epson Corporation
Cache controller
Cache RAM
512 bytes
DMA controller
P0*
P1*
P2*
P3*
P4*
P5*
P6
PD
RTC1S
EXSVD0–1 *
TOUT00–03
TOUT10–13
CAP00–03
CAP10–13
EXCL00–01 *
EXCL10–11 *
USIN0–2
USOUT0–2
MTB
RAM
8K bytes
Flash memory
V
PP
96K bytes
HW processor
(HWP)
RAM
18K bytes
Quad
V
DDQSPI
synchronous
QSDIO00–03
serial interface
QSPICLK0
(QSPI)
#QSPISS0
1 Ch.
Synchronous
SDI0–2
serial interface
SDO0–2
(SPIA)
SPICLK0–2
3 Ch.
#SPISS0–2
I
2
C
SDA0–2
(I2C)
SCL0–2
3 Ch.
IR remote
controller
REMO *
(REMC3)
CLPLS *
1 Ch.
RFIN0 *
R/F converter
REF0 *
(RFC)
SENA0 *
1 Ch.
SENB0 *
RFCLKO0 *
12-bit A/D
#ADTRG0
converter
ADIN00–06 *
(ADC12A)
(ADIN07)
1 Ch.
VREFA0
Temperature
sensor/Reference
voltage generator
(TSRVR)
Sound DAC
SDACOUT_P, P2 *
(SDAC2)
SDACOUT_N, N2 *
1 Ch.
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
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