Epson Arm S1C31 Series Technical Manual page 398

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Address Register name
0x0020 SPIA_1RBFDMAEN
067e (SPIA Ch.1 Receive
Buffer Full DMA
Request Enable
Register)
0x0020 0680–0x0020 068c
Address Register name
0x0020 T16_2CLK
0680 (T16 Ch.2 Clock
Control Register)
0x0020 T16_2MOD
0682 (T16 Ch.2 Mode
Register)
0x0020 T16_2CTL
0684
(T16 Ch.2 Control
Register)
0x0020 T16_2TR
0686 (T16 Ch.2 Reload
Data Register)
0x0020 T16_2TC
0688
(T16 Ch.2 Counter
Data Register)
0x0020 T16_2INTF
068a (T16 Ch.2 Interrupt
Flag Register)
0x0020 T16_2INTE
068c (T16 Ch.2 Interrupt
Enable Register)
0x0020 0690–0x0020 06a8
Address Register name
0x0020 QSPI_0MOD
0690
(QSPI Ch.0 Mode
Register)
0x0020 QSPI_0CTL
0692
(QSPI Ch.0 Control
Register)
0x0020 QSPI_0TXD
0694 (QSPI Ch.0 Transmit
Data Register)
0x0020 QSPI_0RXD
0696
(QSPI Ch.0 Receive
Data Register)
AP-A-36
Bit Bit name
15–8 –
7–4 –
3–0 RBFDMAEN[3:0]
Bit Bit name
15–9 –
8 DBRUN
7–4 CLKDIV[3:0]
3–2 –
1–0 CLKSRC[1:0]
15–8 –
7–1 –
0 TRMD
15–9 –
8 PRUN
7–2 –
1 PRESET
0 MODEN
15–0 TR[15:0]
15–0 TC[15:0]
15–8 –
7–1 –
0 UFIF
15–8 –
7–1 –
0 UFIE
Quad Synchronous Serial Interface (QSPI) Ch.0
Bit Bit name
15–12 CHDL[3:0]
11–8 CHLN[3:0]
7–6 TMOD[1:0]
5 PUEN
4 NOCLKDIV
3 LSBFST
2 CPHA
1 CPOL
0 MST
15–8 –
7–4 –
3 DIR
2 MSTSSO
1 SFTRST
0 MODEN
15–0 TXD[15:0]
15–0 RXD[15:0]
Seiko Epson Corporation
Initial Reset R/W
0x00 – R
0x0 – R
0x0 H0 R/W
16-bit Timer (T16) Ch.2
Initial Reset R/W
0x00 – R
0 H0 R/W
0x0 H0 R/W
0x0 – R
0x0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
0x00 – R
0 H0 R/W
0x00 – R
0 H0 R/W
0 H0 R/W
0xffff H0 R/W
0xffff H0 R
0x00 – R
0x00 – R
0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
Initial Reset R/W
0x7 H0 R/W
0x7 H0 R/W
0x0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x0 – R
0 H0 R/W
1 H0 R/W
0 H0 R/W
0 H0 R/W
0x0000 H0 R/W
0x0000 H0 R
Remarks
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Remarks
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Cleared by writing 1.
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Remarks
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S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)