Operating Mode; Initial Boot Sequence; Transition Between Operating Modes - Epson Arm S1C31 Series Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS

2.4 Operating Mode

2.4.1 Initial Boot Sequence

Figure 2.4.1.1 shows the initial boot sequence after power is turned on.
Reset request from POR
(Initial SYSCLK)
Internal reset signal
SYSRST, H0, H1
Cortex
program counter (PC)
Note: The reset cancelation time at power-on varies according to the power rise time and reset request
cancelation time.
For the reset hold time t
RSTR

2.4.2 Transition between Operating Modes

State transitions between operating modes shown in Figure 2.4.2.1 take place in this IC.
RUN mode
RUN mode refers to the state in which the CPU is executing the program. A transition to this mode takes place
when the system reset request from the system reset controller is canceled. RUN mode is classified into "IOSC
RUN," "OSC1 RUN," "OSC3 RUN," and "EXOSC RUN" by the SYSCLK clock source.
HALT mode
When the Cortex -M0+ core executes the WFI or WFE instruction with the SLEEPDEEP bit of the
®
Cortex -M0+ System Control Register set to 0, it suspends program execution and stops operating. This state
®
is referred to HALT mode in this IC. In this mode, the clock sources and peripheral circuits keep operating.
This mode can be set while no software processing is required and it reduces power consumption as compared
with RUN mode. HALT mode is classified into "IOSC HALT," "OSC1 HALT," "OSC3 HALT," and "EXOSC
HALT" by the SYSCLK clock source.
SLEEP mode
When the Cortex -M0+ core executes the WFI or WFE instruction with the SLEEPDEEP bit of the
®
Cortex -M0+ System Control Register set to 1, it suspends program execution and stops operating. This state is
®
referred to SLEEP mode in this IC. In this mode, the clock sources stop operating as well.
However, the clock source in which the CLGOSC.IOSCSLPC/OSC1SLPC/OSC3SLPC/EXOSCSLPC bit is set
to 0 keeps operating, so the peripheral circuits with the clock being supplied can also operate. By setting this
mode when no software processing and peripheral circuit operations are required, power consumption can be
less than HALT mode.
The RAM retains data even in SLEEP mode.
2-14
V
DD
Undefined
IOSCCLK
Undefined
®
-M0+ core
Figure 2.4.1.1 Initial Boot Sequence
, refer to "Reset hold circuit characteristics" in the "Electrical Characteristics" chapter.
Seiko Epson Corporation
Cancel reset request
Cancel reset request
Reset hold time t
RSTR
∗1 ∗2
∗1: Reset vector (reset handler start address)
∗2: Address (reset vector + 2)
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)