Cache Controller (Cache) - Epson Arm S1C31 Series Technical Manual

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Address Register name
0x0020 CLGOSC3
0048 (CLG OSC3 Control
Register)
0x0020 CLGINTF
004c
(CLG Interrupt Flag
Register)
0x0020 CLGINTE
004e
(CLG Interrupt Enable
Register)
0x0020 CLGFOUT
0050 (CLG FOUT Control
Register)
0x0020 CLGTRIM1
0052 (CLG Oscillation
Frequency Trimming
Register 1)
0x0020 CLGTRIM2
0054
(CLG Oscillation
Frequency Trimming
Register 2)
0x0020 CLGTRIM3
005a (CLG Oscillation
Frequency Trimming
Register 3)
0x0020 0080
Address Register name
0x0020 CACHECTL
0080
(CACHE Control
Register)
AP-A-2
Bit Bit name
15–12 –
11–10 OSC3FQ[1:0]
9 OSC3MD
8 –
7–6 –
5–4 OSC3INV[1:0]
3 OSC3STM
2–0 OSC3WT[2:0]
15–9 –
8 OSC3TERIF
7 –
6 (reserved)
5 OSC1STPIF
4 OSC3TEDIF
3 –
2 OSC3STAIF
1 OSC1STAIF
0 IOSCSTAIF
15–9 –
8 OSC3TERIE
7 –
6 (reserved)
5 OSC1STPIE
4 OSC3TEDIE
3 –
2 OSC3STAIE
1 OSC1STAIE
0 IOSCSTAIE
15–8 –
7 –
6–4 FOUTDIV[2:0]
3–2 FOUTSRC[1:0]
1 –
0 FOUTEN
15–14 –
13–8 IOSCLSAJ[5:0]
7–6 –
5–0 IOSCHSAJ[5:0]
15–8 –
7–6 –
5–0 OSC1SAJ[5:0]
15–9 –
8–0 OSC3SAJ[8:0]
Bit Bit name
15–8 –
7–2 –
1 –
0 CACHEEN
Seiko Epson Corporation
Initial Reset R/W
0x0 – R
0x1 H0 R/WP
0 H0 R/WP
0 – R
0x0 – R
0x3 H0 R/WP
0 H0 R/WP
0x6 H0 R/WP
0x00 – R
0 H0 R/W
0 – R
0 H0 R
0 H0 R/W
0 H0 R/W
0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0 H0 R/W
0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0 – R
0x0 H0 R/W
0x0 H0 R/W
0 – R
0 H0 R/W
0x0 – R
H0 R/WP * Determined by factory
*
0x0 – R
H0 R/WP * Determined by factory
*
0x00 – R
0x0 – R
H0 R/WP * Determined by factory
*
0x00 – R
H0 R/WP * Determined by factory
*

Cache Controller (CACHE)

Initial Reset R/W
0x00 – R
0x00 – R
1 – R
0 H0 R/W
S1C31D41 TECHNICAL MANUAL
Remarks
–
–
Cleared by writing 1.
–
Cleared by writing 1.
–
Cleared by writing 1.
–
–
–
adjustment.
–
adjustment.
–
adjustment.
–
adjustment.
Remarks
–
(Rev. 1.1)