Epson Arm S1C31 Series Technical Manual page 197

15 Quad Synchronous Serial Interface (QSPI)
HCLK
HSEL
HADDR
HTRANS
HSIZE
HREADY
HRDATA
fifo_read_level
QSPI_nMOD register
#QSPISSn
CPOL bit CPHA bit
1 1
QSPICLKn
0 0
QSDIOn[3:0]
HCLK
HSEL
HADDR
HTRANS
HSIZE
HREADY
HRDATA
fifo_read_level
QSPI_nMOD register
#QSPISSn
CPOL bit CPHA bit
1 1
QSPICLKn
0 0
QSDIOn[3:0]
Figure 15.5.6.3 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Non-Sequential Read
15-20
n
2
2
2
#QSPISSn
inactive
period
(TCSH)
Address cycle
(low-order 16 bits)
Seiko Epson Corporation
0
Address cycle
(high-order 8/16 bits)
0
Dummy cycle
Address cycle
(low-order 16 bits)
1
Data cycle Data cycle
(for n) (for n+8)
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
n
0