Epson Arm S1C31 Series Technical Manual page 5

4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-2
4.3 Flash Memory ................................................................................................................. 4-2
4.3.1 Flash Memory Pin ............................................................................................. 4-2
4.3.2 Flash Bus Access Cycle Setting ....................................................................... 4-2
4.3.3 Flash Programming ........................................................................................... 4-2
4.4 RAM ................................................................................................................................ 4-3
4.5 Peripheral Circuit Control Registers ................................................................................ 4-3
4.5.1 System-Protect Function .................................................................................. 4-9
4.6 Instruction Cache ............................................................................................................ 4-9
4.7 Memory Mapped Access Area For External Flash Memory ........................................... 4-9
4.8 Control Registers ............................................................................................................ 4-9
System Protect Register ...................................................................................................... 4-9
CACHE Control Register ..................................................................................................... 4-9
FLASHC Flash Read Cycle Register .................................................................................. 4-10
5 Interrupt .........................................................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Offset Address (VTOR) ................................................................. 5-3
5.2.2 Priority of Interrupts .......................................................................................... 5-3
5.3 Peripheral Circuit Interrupt Control ................................................................................. 5-3
5.4 NMI .................................................................................................................................. 5-4
6 DMA Controller (DMAC) ...............................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 Operations ...................................................................................................................... 6-2
6.2.1 Initialization ....................................................................................................... 6-2
6.3 Priority ............................................................................................................................. 6-2
6.4 Data Structure ................................................................................................................. 6-2
6.4.1 Transfer Source End Pointer ............................................................................. 6-3
6.4.2 Transfer Destination End Pointer ...................................................................... 6-3
6.4.3 Control Data ...................................................................................................... 6-4
6.5 DMA Transfer Mode ........................................................................................................ 6-5
6.5.1 Basic Transfer ................................................................................................... 6-5
6.5.2 Auto-Request Transfer ...................................................................................... 6-5
6.5.3 Ping-Pong Transfer ........................................................................................... 6-6
6.5.4 Memory Scatter-Gather Transfer ...................................................................... 6-7
6.5.5 Peripheral Scatter-Gather Transfer ................................................................... 6-8
6.6 DMA Transfer Cycle ........................................................................................................ 6-9
6.7 Interrupts ......................................................................................................................... 6-9
6.8 Control Registers ........................................................................................................... 6-10
DMAC Status Register ........................................................................................................ 6-10
DMAC Configuration Register ............................................................................................ 6-10
DMAC Control Data Base Pointer Register ........................................................................ 6-11
DMAC Alternate Control Data Base Pointer Register ......................................................... 6-11
DMAC Software Request Register ..................................................................................... 6-11
DMAC Request Mask Set Register .................................................................................... 6-11
DMAC Request Mask Clear Register ................................................................................. 6-12
DMAC Enable Set Register................................................................................................. 6-12
DMAC Enable Clear Register ............................................................................................. 6-12
DMAC Primary-Alternate Set Register ............................................................................... 6-12
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Seiko Epson Corporation
CONTENTS
iii