Epson Arm S1C31 Series Technical Manual page 193

15 Quad Synchronous Serial Interface (QSPI)
By setting the QSPI_nRBFDMAEN.RBFDMAENx
request is sent to the DMA controller and the received data is transferred from the QSPI_nRXD register to the
specified memory via DMA Ch.x
This automates the procedure from Step 3 to Step 9 described above.
The transfer source/destination and control data must be set for the DMA controller and the relevant DMA
channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the "DMA
Controller" chapter.
Table 15.5.5.1 DMA Data Structure Configuration Example (for Writing 16-bit Dummy Transmit Data)
Item
End pointer Transfer source
Transfer destination QSPI_nTXD register address
Control data dst_inc
dst_size
src_inc
src_size
R_power
n_minus_1
cycle_ctrl
Table 15.5.5.2 DMA Data Structure Configuration Example (for 16-bit Data Reception)
Item
End pointer Transfer source
Transfer destination Memory address to which the last received data is stored
Control data dst_inc
dst_size
src_inc
src_size
R_power
n_minus_1
cycle_ctrl
The following shows an example of the control procedure including the DMA controller operations:
1. Configure the primary data structure for the DMA channel (Ch.x) used for writing dummy bytes to the
QSPI_nTXD register as shown in Table 15.5.5.1.
2. Configure the primary data structure for the DMA channel (Ch.y) used for reading data from the QSPI_
nRXD register as shown in Table 15.5.5.2.
3. Enable both the DMA channels using the DMA controller register.
4. Increase the priority of the DMA channel used for reading data using the DMA controller register.
5. Clear the channel request masks for both the DMA channels using the DMA controller register.
6. Clear the DMA transfer completion interrupt flags using the DMA controller register.
7. Enable only the DMA transfer completion interrupt of the DMA channel used for reading using the DMA
controller register.
8. Clear pending DMA interrupts in the CPU.
9. Enable pending DMA interrupts in the CPU.
10. Enable the QSPI to issue DMA transfer requests to both the DMA channels using the QSPI_nTBEDMAEN.
TBEDMAENx and QSPI_nRBFDMAEN.RBFDMAENy bits.
11. Assert the slave select signal by controlling the QSPI_nCTL.MSTSSO bit, or the general-purpose output
port used for an extra slave select signal output (if necessary).
12. Issue a software DMA transfer request to the DMA channel used for writing dummy bytes by setting the
DMA controller register. This operation is required to read the first data and to set the receive buffer full
status flag. Once the receive buffer full status flag is set, a hardware DMA request is generated, and the
DMA controller transfers data from the QSPI_nRXD register and then writes another dummy byte to the
QSPI_nTXD register, allowing the QSPI to read the next data.
13. Wait for a DMA interrupt.
15-16
bit to 1 (DMA transfer request enabled), a DMA transfer
2
when the QSPI_nINTF.RBFIF bit is set to 1 (receive buffer full).
2
Memory address in which dummy data is stored
0x3 (no increment)
0x1 (haflword)
0x3 (no increment)
0x1 (halfword)
0x0 (arbitrated for every transfer)
Number of transfer data
0x1 (basic transfer)
QSPI_nRXD register address
0x1 (+2)
0x1 (haflword)
0x3 (no increment)
0x1 (halfword)
0x0 (arbitrated for every transfer)
Number of transfer data
0x1 (basic transfer)
Seiko Epson Corporation
Setting example
Setting example
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)