N State Monitor Register - Epson Arm S1C31 Series Technical Manual

Bits 15–0 PITCH[15:0]
These bits specify the playback pitch (or musical interval).
When converting the pitch in combination with speed conversion, the pitch setting value should be
specified within the range shown in Table 22.6.1.8.
When converting the pitch alone without speed conversion, the SPEED_0.SPEED[15:0] bits should be
set to 0x00 and the pitch setting value should be specified within the range shown in Table 22.6.1.9.
Table 22.6.1.8 Pitch Setting (0x55 ≤ SPEED_0.SPEED[15:0] bits ≤ 0x73)
Table 22.6.1.9 Pitch Setting (SPEED_0.SPEED[15:0] bits = 0x00)
Table 22.6.1.10 6.1.10 Setting Values to Convert Speed and Pitch Simultaneously
0x7d 125%
0x78 120%
0x73 115%
0x6e 110%
0x69 105%
SPEED_0.
0x64 100%
SPEED[15:0]
0x5f 95%
bits
0x5a 90%
0x55 85%
0x50 80%
0x4b 75%
0x00 –
Ch.n State Monitor Register
Register name Bit
STATE_n 15–0 STATE[15:0]
(Sound Play)
Bits 15–0 STATE[15:0]
These bits indicate the current state of the Sound Play function.
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
PITCH_0.PITCH[15:0] bits
0x6e
0x69
0x64
0x5f
0x5a
Other
PITCH_0.PITCH[15:0] bits
0x7d
0x78
0x73
0x6e
0x69
0x64
0x5f
0x5a
0x55
0x50
0x4b
Other
0x7d 0x78 0x73 0x6e
125% 120% 115% 110% 105% 100%
– – –
– – –
– – –
– – –
– – –
– – –
– – –
– – –
– – –
– – –
– – –
✓ ✓ ✓
Bit name Initial
Seiko Epson Corporation
22 HW Processor (HWP) and Sound Output (SDAC2)
Pitch
110%
105%
100% Standard pitch
95%
90%
Setting prohibited
Pitch
125%
120%
115%
110%
105%
100% Standard pitch
95%
90%
85%
80%
75%
Setting prohibited
PITCH_0.PITCH[15:0] bits
0x69 0x64 0x5f
95%
– – – –
– – – –
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
✓ ✓ ✓ ✓
– – – –
– – – –
✓ ✓ ✓ ✓
Reset R/W
x – R –
High
↑
↓
Low
High
↑
↓
Low
0x5a 0x55 0x50 0x4b
90% 85% 80% 75%
– – – –
– – – –
– – –
✓
– – –
✓
– – –
✓
– – –
✓
– – –
✓
– – –
✓
– – –
✓
– – – –
– – – –
✓ ✓ ✓ ✓
Remarks
0x00
–
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
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