Hwp Operating Clock; Clock Supply In Sleep Mode; Clock Supply In Debug Mode - Epson Arm S1C31 Series Technical Manual

Cmos 32-bit single chip microcontroller
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22 HW Processor (HWP) and Sound Output (SDAC2)
Figures 22.2.2.3 and 22.2.2.4 show examples to connect the SDAC2 sound signals to an external amplifier circuit
composed of discrete parts. For more information on the amplifier circuit configuration, refer to an evaluation man-
ual or application note.
Two-pin output mode
Figure 22.2.2.3 Connection Example of SDAC2 with External Discrete Amplifier Circuit (Two-pin Output Mode)
Four-pin output mode
Figure 22.2.2.4 Connection Example of SDAC2 with External Discrete Amplifier Circuit (Four-pin Output Mode)
22.3 Clock Settings

22.3.1 HWP Operating Clock

The HWP and the SDAC2 used for the Sound Play function operate with the SYSCLK (system clock) supplied
from the clock generator. The HWP operating clock should be controlled as in the procedure shown below.
When executing the Sound Play function
1. Configure SYSCLK in the clock generator (refer to "Clock Generator" in the "Power Supply, Reset, and
Clocks" chapter).
- SYSCLK source = OSC3
- OSC3 oscillation frequency = 16 MHz
2. Set the following SDAC2CLK register bits (set in S1C31D41 regardless of the sound output destination):
- Set the SDAC2CLK.CLKSRC[1:0] bits to 0x02. (Clock source = OSC3)
- Set the SDAC2CLK.CLKDIV[1:0] bits to 0x0. (Clock division ratio = 1/1)
When executing the Memory Check function
1. Configure SYSCLK for operating the Memory Check function in the clock generator (refer to "Clock Gen-
erator" in the "Power Supply, Reset, and Clocks" chapter).
The Memory Check function allows the HWP to use SYSCLK at any arbitrary frequency.

22.3.2 Clock Supply in SLEEP Mode

The HWP and SDAC2 stop operating in SLEEP mode, as the SYSCLK stops. Do not put the IC into SLEEP mode
while the HWP is operating. It is possible to put the IC into HALT mode while the HWP is operating.

22.3.3 Clock Supply in DEBUG Mode

The sound play and Memory Check functions can operate even in DEBUG mode, as SYSCLK is supplied.
The SYSCLK supply to the SDAC2 during DEBUG mode can be controlled using the SDAC2CLK.DBRUN bit.
The SDAC2CLK.DBRUN bit must be set to 1 when using the Sound Play function during DEBUG mode. Be
aware that the sound cannot be output normally when SDAC2CLK.DBRUN bit = 0.
22-4
SDACOUT_N
Amplifier circuit
(composed of
discrete parts)
SDACOUT_P
S1C31 SDAC
* SDAC2MOD.PWMMODE[1:0] bits = 0x3
SDACOUT_N2
Amplifier circuit
SDACOUT_N
(composed of
SDACOUT_P2
discrete parts)
SDACOUT_P
S1C31 SDAC
* SDAC2MOD.PWMMODE[1:0] bits = 0x3
Seiko Epson Corporation
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)

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