T16 Ch.n Interrupt Enable Register - Epson Arm S1C31 Series Technical Manual

T16 Ch.n Interrupt Enable Register

Register name Bit
T16_nINTE 15–8 –
7–1 –
0
Bits 15–1 Reserved
Bit 0 UFIE
This bit enables T16 Ch.n underflow interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be
cleared before enabling interrupts.
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Bit name Initial
0x00
0x00
UFIE 0
Seiko Epson Corporation
Reset R/W
– R –
– R
H0 R/W
12 16-BIT TIMERS (T16)
Remarks
12-7