0X4302: Interrupt Enable Register (Itc_En) - Epson S1C17001 Technical Manual

0x4302: Interrupt Enable Register (ITC_EN)

Register name Address Bit
Interrupt 0x4302 D15
Enable Register (16 bits)
D14
(ITC_EN)
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D[15:0] IIEN[7:0], EIEN[7:0]: Interrupt Enable Bits
These bits permit or prohibit interrupt events.
1 (R/W): Interrupt permitted
0 (R/W): Interrupt prohibited (default)
Setting the interrupt enable bit to 1 permits interrupts. Setting it to 0 prohibits interrupts.
Even if interrupt prohibition has been set, the corresponding interrupt can still be used to cancel Stand-
by mode.
Table 6.7.4: Hardware interrupt factors and interrupt enable bits
Interrupt enable bit
EIEN0 (D0)
EIEN1 (D1)
EIEN2 (D2)
EIEN3 (D3)
EIEN4 (D4)
EIEN7 (D7)
IIEN0 (D8)
IIEN1 (D9)
IIEN2 (D10)
IIEN3 (D11)
IIEN4 (D12)
IIEN5 (D13)
IIEN6 (D14)
IIEN7 (D15)
S1C17001 TECHNICAL MANUAL
Name Function
IIEN7 I 2 C interrupt enable
IIEN6 SPI interrupt enable
IIEN5 Remote controller interrupt enable
IIEN4 UART interrupt enable
IIEN3 16-bit timer Ch.2 interrupt enable
IIEN2 16-bit timer Ch.1 interrupt enable
IIEN1 16-bit timer Ch.0 interrupt enable
IIEN0 8-bit timer interrupt enable
EIEN7 PWM&capture timer interrupt en-
able
EIEN6 reserved
EIEN5 reserved
EIEN4 8-bit OSC1 timer interrupt enable
EIEN3 Clock timer interrupt enable
EIEN2 Stopwatch timer interrupt enable
EIEN1 P1 port interrupt enable
EIEN0 P0 port interrupt enable
P0 port interrupt: P00 to P07 port input
P1 port interrupt: P10 to P17 port input
Stopwatch timer interrupt: 100 Hz/10 Hz/1 Hz signal
Clock timer interrupt: 32 Hz/8 Hz/2 Hz/1 Hz signal
8-bit OSC1 timer interrupt: Compare match
PWM & capture timer interrupt: Compare A/Compare B match
8-bit timer interrupt: Timer underflow
16-bit timer Ch.0 interrupt: Timer underflow
16-bit timer Ch.1 interrupt: Timer underflow
16-bit timer Ch.2 interrupt: Timer underflow
UART interrupt: Transmit buffer empty/Receive buffer full/Receive error
Remote controller interrupt: Data length counter underflow/Input rise-up/Input drop-
off
SPI interrupt: Transmit buffer empty/Receive buffer full
I 2 C interrupt: Transmit buffer empty/Receive buffer full
EPSON
6 INITERRUPT CONTROLLER
Setting
1 Enable 0 Disable
Hardware interrupt factor
Init. R/W Remarks
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
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