Epson S1C17001 Technical Manual page 191

15 CLOCK TIMER (TC)
EIFT3 is set to 1 at the falling edge of the 32/8/2/1 Hz signals for which interrupts are permitted by the CT
module. If EIEN3 is set to 1 here, the ITC sends an interrupt request to the S1C17 core. To prevent clock timer
interrupts, set the EIEN3 to 0. EIFT3 is set to 1 by the interrupt signal from the CT module regardless of the
EIEN3 setting (even if it is set to 0).
EILV3[2:0] sets the clock timer interrupt level (0 to 7).
The S1C17 core accepts interrupts when the following conditions are satisfied:
• The interrupt enable bit has been set to 1.
• The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit has been set to 1.
• The clock timer interrupt has been set to a higher interrupt level than that set for the PSR IL (interrupt level).
• No other interrupt factors having higher precedence (e.g., NMI) are present.
For detailed information on these interrupt control registers and operations when interrupts occur, refer to "6
Interrupt Controller (ITC)."
Note: The following processes must be performed to manage the interrupt factor occurrence state
using the CT module interrupt flag.
1. Set the clock timer interrupt trigger mode to level trigger mode.
2. Reset the CT module interrupt flags CTIF* within the interrupt processing routine after the
interrupt occurs (this also resets the ITC interrupt flag).
Interrupt vectors
The clock timer interrupt vector numbers and vector addresses are listed below.
Vector number: 7 (0x07)
Vector address: 0x801c
182
EPSON
S1C17001 TECHNICAL MANUAL