Debug Break Operation Status - Epson S1C17001 Technical Manual

22 ON-CHIP DEBUGGER (DBG)

22.2 Debug Break Operation Status

The S1C17 core switches to debug mode when the brk command is executed or a debug interrupt is generated by
a break signal (Low) input to the DSIO pin. This state persists until the retd command is executed.
During this time, hardware interrupts and NMIs are disabled.
The default setting halts peripheral circuit operations. This setting can be modified even when debugging is under-
way.
Peripheral circuits that operate using the prescaler output clock
• 8-bit timer
• 16-bit timer
• PWM & capture timer
• Remote controller
• P port
• UART
• SPI
• I C
2
With the default settings, the prescaler will stop in debug mode, also stopping the peripheral circuits above that
use the prescaler output clock. The prescaler includes PRUND (D1/PSC_CTL register) to specify prescaler
operations during debug mode. When PRUND is set to 1, the prescaler operates even in debug mode, allowing
the peripheral circuits above to operate as well. When PRUND is 0 (default), the prescaler and the peripheral
circuits above will stop when the S1C17 core switches to debug mode.
∗ PRUND: Prescaler Run/Stop Setting (in Debug Mode) Bit in the Prescaler Control (PSC_CTL) Register
(D1/0x4020)
Peripheral circuits that operate using the OSC1 clock
• Clock timer
• Watchdog timer
• Stopwatch timer
The MISC register includes O1DBG (D0/MISC_OSC1 register) to specify the operation of the above OSC1
peripheral circuits during debug mode. When O1DBG is set to 1, the OSC1 peripheral circuits operate even in
debug mode. When O1DBG is 0 (default), the OSC1 peripheral circuits will stop when the S1C17 core switch-
es to debug mode.
∗ O1DBG: OSC1 Peripheral Control (in Debug Mode) Bit in the OSC1 Peripheral Control (MISC_OSC1)
Register (D0/0x5322)
The 8-bit OSC1 timer does not stop in debug mode, even if O1DBG is set to 1.
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S1C17001 TECHNICAL MANUAL