0X5080: Pclk Control Register (Clg_Pclk) - Epson S1C17001 Technical Manual

0x5080: PCLK Control Register (CLG_PCLK)

Register name Address Bit
PCLK Control 0x5080 D7–2 –
Register (8 bits)
D1–0 PCKEN[1:0] PCLK enable
(CLG_PCLK)
D[7:2] Reserved
D[1:0] PCKEN[1:0]: PCLK Enable Bits
Permit or prohibit clock (PCLK) feed to internal peripheral modules.
The PCKEN[1:0] default setting is 0x3, which enables clock feed. Stop the clock feed to reduce power
consumption if the peripheral modules listed below are not required.
Peripheral modules operated using PCLK
• Prescaler (PWM & capture timer, remote controller, P port)
• UART
• 8-bit timer
• 16-bit timer Ch.0 to 2
• Interrupt controller
• SPI
• I 2 C
• P port & port MUX
• PWM & capture timer
• MISC register
• Remote controller
Since the following peripheral modules are not operated using PCLK except for control register access,
PCLK is not required after setting the control register to start operations.
• Clock timer
• Stopwatch timer
• Watchdog timer
• 8-bit OSC1 timer
Note: Do not set PCKEN[1:0] to 0x2 or 0x1, since doing so will stop the operation of certain pe-
ripheral modules.
S1C17001 TECHNICAL MANUAL
Name Function
reserved
Table 8.4.2: PCLK control
PCKEN[1:0]
0x3
0x2
0x1
0x0
EPSON
8 CLOCK GENERATOR (CLG)
Setting
–
PCKEN[1:0] PCLK supply
0x3 Enable
0x2 Not allowed
0x1 Not allowed
0x0 Disable
PCLK feed
Permitted (on)
Setting prohibited
Setting prohibited
Prohibited (off)
(Default: 0x3)
Init. R/W Remarks
– – 0 when being read.
0x3 R/W
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