Fine Mode - Epson S1C17001 Technical Manual

12 8-BIT TIMER (T8F)

12.8 Fine Mode

Fine mode provides a function that minimizes transfer rate errors.
The 8-bit timer can output a programmable clock signal for use as the UART serial transfer clock. The timer output
clock can be set to the required frequency by selecting the appropriate prescaler output clock and reload data. Note
that errors may occur, depending on the transfer rate. Fine mode extends the output clock cycle by delaying the un-
derflow pulse from the counter. This delay can be specified with the TFMD[3:0] bit (D[11:8]/T8F_CTL register).
∗ TFMD[3:0]: Fine Mode Setup Bits in the 8-bit Timer Control (T8F_CTL) Register (D[11:8]/0x4206)
The TFMD[3:0] bit specifies the delay pattern to be inserted into the 16 underflow intervals. Inserting one delay
extends the output clock cycle by one count clock cycle. This setting delays the interrupt timing in the same way.
TFMD[3:0]
1 2
0x0 – –
0x1 – –
0x2 – –
0x3 – –
0x4 – –
0x5 – –
0x6 – –
0x7 – –
0x8 – D
0x9 – D
0xa – D
0xb – D
0xc – D
0xd – D
0xe – D
0xf – D
Underflow signal (no correction)
Underflow signal (with correction)
Output clock (no correction)
Output clock (with correction)
After the initial resetting, TFMD[3:0] is set to 0x0, preventing insertion of delay cycles.
132
Table 12.8.1: Delay patterns specified by TFMD[3:0]
3 4 5 6 7
– – – – –
– – – – –
– – – – –
– – – – –
– D – – –
– D – – –
– D – D –
– D – D –
– D – D –
– D – D –
– D – D D
– D – D D
D D – D D
D D – D D
D D D D D
D D D D D
Count clock
15
15
Figure 12.8.1: Delay cycle insertion in Fine mode
EPSON
Underflow number
8 9 10 11
– – – –
– – – –
D – – –
D – – –
D – – –
D – – –
D – – –
D – D –
D – D –
D – D –
D – D –
D – D D
D – D D
D – D D
D – D D
D D D D
D: Indicates the insertion of a delay cycle.
16
16
Delay
12 13 14 15
– – – –
– – – –
– – – –
D – – –
D – – –
D – D –
D – D –
D – D –
D – D –
D – D D
D – D D
D – D D
D – D D
D D D D
D D D D
D D D D
1
1
S1C17001 TECHNICAL MANUAL
16
–
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D