0X5081: Cclk Control Register (Clg_Cclk) - Epson S1C17001 Technical Manual

8 CLOCK GENERATOR (CLG)

0x5081: CCLK Control Register (CLG_CCLK)

Register name Address Bit
CCLK Control 0x5081 D7–2 –
Register (8 bits)
D1–0 CCLK-
(CLG_CCLK)
D[7:2] Reserved
D[1:0] CCLKGR[1:0]: CCLK Clock Gear Ratio Select Bits
Select the gear ratio for reducing system clock speed and set the CCLK clock speed for operating the
S1C17 core. To reduce power consumption, operate the S1C17 core using the slowest possible clock
speed.
76
Name Function
reserved
CCLK clock gear ratio select
GR[1:0]
Table 8.4.3: CCLK gear ratio selection
CCLKGR[1:0]
0x3
0x2
0x1
0x0
Setting
–
CCLKGR[1:0]
0x3
0x2
0x1
0x0
Gear ratio
1/8
1/4
1/2
1/1
(Default: 0x0)
EPSON
Init. R/W Remarks
– – 0 when being read.
Gear ratio 0x0 R/W
1/8
1/4
1/2
1/1
S1C17001 TECHNICAL MANUAL