0X4326: Spi Control Register (Spi_Ctl) - Epson S1C17001 Technical Manual

19 SPI

0x4326: SPI Control Register (SPI_CTL)

Register name Address Bit
SPI Control 0x4326 D15–6 –
Register (16 bits)
D5
(SPI_CTL)
D4
D3
D2
D1
D0
D[15:6] Reserved
D5 SPRIE: Receive Data Buffer Full Interrupt Enable Bit
D5 SPRIE: Receive Data Buffer Full Interrupt Enable Bit
Permits or prohibits receive data buffer full SPI interrupts.
1 (R/W): Permitted
0 (R/W): Prohibited (default)
Setting SPRIE to 1 permits the output of SPI interrupt requests to the ITC due to a receive data buffer
full. These interrupt requests are generated when the data received in the shift register is transferred to
the receive data buffer (when receipt is complete).
SPI interrupts are not generated by receive data buffer full if SPRIE is set to 0.
D4 SPTIE: Transmit Data Buffer Empty Interrupt Enable Bit
Permits or prohibits transmit data buffer empty SPI interrupts.
1 (R/W): Permitted
0 (R/W): Prohibited (default)
Setting SPTIE to 1 permits the output of SPI interrupt requests to the ITC due to a transmit data buffer
empty. These interrupt requests are generated when the data written to the transmit data buffer is trans-
ferred to the shift register (when transmission starts).
SPI interrupts are not generated by transmit data buffer empty if SPTIE is set to 0.
D3 CPHA: SPI Clock Phase Select Bit
Selects the SPI clock phase. (Default: 0)
Sets the data transfer timing together with CPOL (D2). (See Figure 19.7.1.)
D2 CPOL: SPI Clock Polarity Select Bit
Selects the SPI clock polarity.
1 (R/W): Active Low
0 (R/W): Active High (default)
Sets the data transfer timing together with CPHA (D3). (See Figure 19.7.1.)
SPICLK(CPOL = 1, CPHA = 1)
SPICLK(CPOL = 1, CPHA = 0)
SPICLK(CPOL = 0, CPHA = 1)
SPICLK(CPOL = 0, CPHA = 0)
Receive data load timing
to shift register
246
Name Function
reserved
SPRIE Receive data buffer full int. enable 1 Enable
SPTIE Transmit data buffer empty int.
enable
CPHA Clock phase select
CPOL Clock polarity select
MSSL Master/slave mode select
SPEN SPI enable
SDI/SDO
D7 (MSB)
Figure 19.7.1: Clock and data transfer timing
Setting
–
0 Disable
1 Enable 0 Disable
1 Data out 0 Data in
1 Active L 0 Active H
1 Master 0 Slave
1 Enable 0 Disable
EPSON
Init. R/W Remarks
– – 0 when being read.
0 R/W
0 R/W
0 R/W These bits must be
set before setting
0 R/W
SPEN to 1.
0 R/W
0 R/W
D0 (LSB)
S1C17001 TECHNICAL MANUAL