Carrier Generation - Epson S1C17001 Technical Manual

Cmos 16-bit single chip microcontroller
Table of Contents

Advertisement

21.3 Carrier Generation

The REMC module incorporates a carrier generation circuit that generates a carrier signal for transmission in ac-
cordance with the clock set by the software and carrier H and L section lengths.
The prescaler output clock is used for the carrier signal generation clock. The prescaler generates 15 different
clocks, dividing the PCLK clock from 1/1 to 1/16K. One is selected by CGCLK[3:0] (D[7:4]/REMC_PSC regis-
ter).
∗ CGCLK[3:0]: Carrier Generator Clock Select Bits in the REMC Prescaler Clock Select (REMC_PSC) Register
(D[7:4]/0x5341)
CGCLK[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
For more information on prescaler control, refer to "9 Prescaler (PSC)."
Note: The prescaler must run before the REMC module.
The carrier H and L section lengths are set by REMCH[5:0] (D[5:0]/REMC_CARH register) and REMCL[5:0]
(D[5:0]/REMC_CARL register), respectively. These registers set a value corresponding to the number of clock
cycles selected above + 1.
∗ REMCH[5:0]: H Carrier Length Setup Bits in the REMC H Carrier Length Setup (REMC_CARH) Register (D[5:0]/
0x5342)
∗ REMCL[5:0]: L Carrier Length Setup Bits in the REMC L Carrier Length Setup (REMC_CARL) Register
(D[5:0]/0x5343)
The carrier H and L section lengths can be calculated as follows:
Carrier H section length = —————— [s]
Carrier L section length = —————— [s]
REMCH: Carrier H section length register data value
REMCL: Carrier L section length register data value
clk_in:
Prescaler output clock frequency
The carrier signal is generated from these settings as shown in Figure 21.3.1.
Example: CGCLK[3:0] = 0x2 (PCLK-1/4), REMCH[5:0] = 2, REMCL[5:0] = 1
PSC output clock
Count
Carrier
S1C17001 TECHNICAL MANUAL
Table 21.3.1: Carrier generation clock selection
Prescaler output clock
Reserved
PCLK-1/16384
PCLK-1/8192
PCLK-1/4096
PCLK-1/2048
PCLK-1/1024
PCLK-1/512
PCLK-1/256
REMCH + 1
clk_in
REMCL + 1
clk_in
PCLK
0
Carrier H section length
Figure 21.3.1: Carrier signal generation
CGCLK[3:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
1
2
0
Carrier L section length
EPSON
21 REMOTE CONTROLLER (REMC)
Prescaler output clock
PCLK-1/128
PCLK-1/64
PCLK-1/32
PCLK-1/16
PCLK-1/8
PCLK-1/4
PCLK-1/2
PCLK-1/1
(Default: 0x0)
1
0
271

Advertisement

Table of Contents
loading

Table of Contents