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19 SPI
19.6 SPI Interrupts
The SPI module includes a function for generating the following two different interrupt types.
• Transmit buffer empty interrupt
• Receive buffer full interrupt
The SPI module outputs one interrupt signal shared by the three above interrupt factor types to the interrupt con-
troller (ITC). Inspect the status flag to determine the interrupt factor occurring.
Transmit buffer empty interrupt
To use this interrupt, set SPTIE (D4/SPI_CTL register) to 1. If SPTIE is set to 0 (default), interrupt requests for
this factor will not be sent to the ITC.
∗ SPTIE: Transmit Data Buffer Empty Interrupt Enable Bit in the SPI Control (SPI_CTL) Register (D4/0x4326)
When transmission data written to the transmit data buffer is transferred to the shift register, the SPI module
sets the SPTBE bit (D0/SPI_ST register) to 1, indicating that the transmit data buffer is empty. If transmit buf-
fer empty interrupts are permitted (SPTIE = 1), an interrupt request pulse is sent simultaneously to the ITC.
∗ SPTBE: Transmit Data Buffer Empty Flag in the SPI Status (SPI_ST) Register (D0/0x4320)
An interrupt occurs if other interrupt conditions are met.
You can inspect the SPTBE flag in the SPI interrupt processing routine to determine whether the SPI interrupt
is attributable to a transmit buffer empty. If SPTBE is 0, the next transmission data can be written to the trans-
mit data buffer by the interrupt processing routine.
Receive buffer full interrupt
To use this interrupt, set SPRIE (D5/SPI_CTL register) to 1. If SPRIE is set to 0 (default), interrupt requests for
this factor will not be sent to the ITC.
∗ SPRIE: Receive Data Buffer Full Interrupt Enable Bit in the SPI Control (SPI_CTL) Register (D5/0x4326)
When data received in the shift register is loaded into the receive data buffer, the SPI module sets the SPRBF
bit (D1/SPI_ST register) to 1, indicating that the receive data buffer contains readable received data. If receive
buffer full interrupts are permitted (SPRIE = 1), an interrupt request pulse is output to the ITC at the same time.
∗ SPRBF: Receive Data Buffer Full Flag in the SPI Status (SPI_ST) Register (D1/0x4320)
An interrupt occurs if other interrupt conditions are met.
You can inspect the SPRBF flag in the SPI interrupt processing routine to determine whether the SPI interrupt
is attributable to a receive buffer full. If SPRBF is 1, the received data can be read from the receive data buffer
by the interrupt processing routine.
SPI interrupt ITC registers
The control bits for the SPI module in the ITC are listed below.
Interrupt flag
∗ IIFT6: SPI Interrupt Flag in the Interrupt Flag (ITC_IFLG) Register (D14/0x4300)
Interrupt enable bit
∗ IIEN6: SPI Interrupt Enable Bit in the Interrupt Enable (ITC_EN) Register (D14/0x4302)
Interrupt level setting bit
∗ IILV6[2:0]: SPI Interrupt Level Bits in the Internal Interrupt Level Setup (ITC_ILV3) Register 3 (D[2:0]/0x4314)
If an interrupt request pulse is output by the SPI module, the IIFT6 interrupt flag is set to 1.
If the IIEN6 interrupt enable bit is set to 1, the ITC sends an interrupt request to the S1C17 core. To prohibit
SPI interrupts, set IIEN6 to 0.
The IIFT6 flag is set to 1 by a SPI interrupt request pulse, regardless of the IIEN6 bit setting (i.e., even if set to 0).
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S1C17001 TECHNICAL MANUAL
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