0X4103: Uart Mode Register (Uart_Mod) - Epson S1C17001 Technical Manual

18 UART

0x4103: UART Mode Register (UART_MOD)

Register name Address Bit
UART Mode 0x4103 D7–5 –
Register (8 bits)
D4
(UART_MOD)
D3
D2
D1
D0
D[7:5] Reserved
D4 CHLN: Character Length Select Bit
Selects the serial transfer data length.
1 (R/W): 8 bits
0 (R/W): 7 bits (default)
D3 PREN: Parity Enable Bit
Enables the parity function.
1 (R/W): With parity
0 (R/W): No parity (default)
PREN is used to select receive data parity checking and to determine whether a parity bit is added to
transmitted data. Setting PREN to 1 parity-checks the received data. A parity bit is automatically added
to the transmitted data. If PREN is set to 0, no parity bit is checked or added.
D2 PMD: Parity Mode Select Bit
Selects the parity mode.
1 (R/W): Odd parity
0 (R/W): Even parity (default)
Writing 1 to PMD selects odd parity; writing 0 to it selects even parity. Parity checking and parity bit
addition are enabled only when PREN (D3) is set to 1. The PMD setting is disabled if PREN (D3) is 0.
D1 STPB: Stop Bit Select Bit
Selects the stop bit length.
1 (R/W): 2 bits
0 (R/W): 1 bit (default)
Writing 1 to STPB selects two stop bits; writing 0 to it selects one bit. The start bit is fixed at one bit.
D0 SSCK: Input Clock Select Bit
Selects the input clock.
1 (R/W): External clock (SCLK)
0 (R/W): Internal clock (default)
Selects whether the internal clock (8-bit timer output clock) or external clock (input via SCLK pin) is
used. Writing 1 to SSCK selects the external clock; Writing 0 to it selects the internal clock.
228
Name Function
reserved
CHLN Character length
PREN Parity enable
PMD Parity mode select
STPB Stop bit select
SSCK Input clock select
Setting
–
1 8 bits 0 7 bits
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 External 0 Internal
EPSON
Init. R/W Remarks
– – 0 when being read.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
S1C17001 TECHNICAL MANUAL