0X5002: Clock Timer Interrupt Mask Register (Ct_Imsk) - Epson S1C17001 Technical Manual

15 CLOCK TIMER (TC)

0x5002: Clock Timer Interrupt Mask Register (CT_IMSK)

Register name Address Bit
Clock Timer 0x5002 D7–4 –
Interrupt Mask (8 bits)
D3
Register
D2
(CT_IMSK)
D1
D0
This register permits or prohibits interrupt requests individually for the clock timer 32 Hz, 8 Hz, 2 Hz, and 1 Hz
signals. Setting the CTIE*bit to 1 permits clock timer interrupts for the corresponding frequency signal falling
edge, while setting to 0 prohibits interrupts.
To enable interrupt generation, the ITC clock timer interrupt enable bits must also be set to permit interrupts.
D[7:4] Reserved
D3 CTIE32: 32 Hz Interrupt Enable Bit
Permits or prohibits 32 Hz signal interrupts.
1 (R/W): Interrupt permitted
0 (R/W): Interrupt prohibited (default)
D2 CTIE8: 8 Hz Interrupt Enable Bit
Permits or prohibits 8 Hz signal interrupts.
1 (R/W): Interrupt permitted
0 (R/W): Interrupt prohibited (default)
D1 CTIE2: 2 Hz Interrupt Enable Bit
Permits or prohibits 2 Hz signal interrupts.
1 (R/W): Interrupt permitted
0 (R/W): Interrupt prohibited (default)
D0 CTIE1: 1 Hz Interrupt Enable Bit
Permits or prohibits 1 Hz signal interrupts.
1 (R/W): Interrupt permitted
0 (R/W): Interrupt prohibited (default)
186
Name Function
reserved
CTIE32 32 Hz interrupt enable
CTIE8 8 Hz interrupt enable
CTIE2 2 Hz interrupt enable
CTIE1 1 Hz interrupt enable
Setting
–
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
EPSON
Init. R/W Remarks
– – 0 when being read.
0 R/W
0 R/W
0 R/W
0 R/W
S1C17001 TECHNICAL MANUAL