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10.3 Data Input/Output
The input/output ports permit selection of the data input/output direction for each bit using PxIO[7:0] (Px_IO regis-
ter).
∗ P0IO[7:0]: P0[7:0] Port I/O Direction Select Bits in the P0 Port I/O Direction Control (P0_IO) Register (D[7:0]/0x5202)
∗ P1IO[7:0]: P1[7:0] Port I/O Direction Select Bits in the P1 Port I/O Direction Control (P1_IO) Register (D[7:0]/0x5212)
∗ P2IO[7:0]: P2[7:0] Port I/O Direction Select Bits in the P2 Port I/O Direction Control (P2_IO) Register (D[7:0]/0x5222)
∗ P3IO[3:0]: P3[3:0] Port I/O Direction Select Bits in the P3 Port I/O Direction Control (P3_IO) Register (D[3:0]/0x5232)
The input/output direction for the port selecting the peripheral module function is controlled by the peripheral mod-
ule. The PxIO[7:0] setting is ignored.
Data input
When set to input mode, PxIO[7:0] is set to 0 (default). The input/output port set to input mode switches to
high-impedance state, and functions as the input port. If pull-up is enabled by the Px_PU register, the port will
be pulled up.
In input mode, the input pin state can be read out directly from PxIN[7:0] (Px_IN register). The value read will
be 1 when the input pin is at High (HV
∗ P0IN[7:0]: P0[7:0] Port Input Data Bits in the P0 Port Input Data (P0_IN) Register (D[7:0]/0x5200)
∗ P1IN[7:0]: P1[7:0] Port Input Data Bits in the P1 Port Input Data (P1_IN) Register (D[7:0]/0x5210)
∗ P2IN[7:0]: P2[7:0] Port Input Data Bits in the P2 Port Input Data (P2_IN) Register (D[7:0]/0x5220)
∗ P3IN[3:0]: P3[3:0] Port Input Data Bits in the P3 Port Input Data (P3_IN) Register (D[3:0]/0x5230)
Data output
When set to output mode, PxIO[7:0] is set to 1. The input/output port set to output mode functions as the output
port, while the port pin outputs High (HV
Low (V
) level if written as 0. Note that the port will not be pulled up in output mode even if pull-up is en-
SS
abled by the Px_PU register.
∗ P0OUT[7:0]: P0[7:0] Port Output Data Bits in the P0 Port Output Data (P0_OUT) Register (D[7:0]/0x5201)
∗ P1OUT[7:0]: P1[7:0] Port Output Data Bits in the P1 Port Output Data (P1_OUT) Register (D[7:0]/0x5211)
∗ P2OUT[7:0]: P2[7:0] Port Output Data Bits in the P2 Port Output Data (P2_OUT) Register (D[7:0]/0x5221)
∗ P3OUT[3:0]: P3[3:0] Port Output Data Bits in the P3 Port Output Data (P3_OUT) Register (D[3:0]/0x5231)
Writing to PxOUT[7:0] is possible without affecting pin status, even in input mode.
S1C17001 TECHNICAL MANUAL
) level and 0 when it is at Low (V
DD
) level if PxOUT[7:0] (Px_OUT register) is written as 1 and outputs
DD
EPSON
10 INPUT/OUTPUT PORT (P)
) level.
SS
85
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