Oscillator Circuit (Osc); Osc Module Configuration - Epson S1C17001 Technical Manual

7 Oscillator Circuit (OSC)

7.1 OSC Module Configuration

The S1C17001 incorporates two internal oscillator circuits (OSC3 and OSC1). The OSC3 oscillator circuit gener-
ates the main clock (max. 8.2 MHz) for high-speed operation of the S1C17 core and peripheral circuits. The OSC1
oscillator circuit generates a sub-clock (typ. 32.768 kHz) for timer and low-power operations.
The OSC3 clock is selected as the system clock after initial resetting.
Oscillator circuit on/off switching and system clock selection (between OSC3 and OSC1) is controlled by software.
External clock output is also possible.
Figure 7.1.1 illustrates the clock system and OSC module configuration.
SLEEP, on/off control
OSC3
OSC3
oscillator circuit
(8.2 MHz)
OSC4
FOUT3
FOUT3
output circuit
On/off control
SLEEP, on/off control
OSC1
OSC1
oscillator circuit
(32.768 kHz)
OSC2
FOUT1
FOUT1
output circuit
On/off control
Noise filter
RESET
On/off control
Noise filter
NMI
On/off control
To reduce power consumption, control the clock in conjunction with processing and use standby mode. For more
information on reducing power consumption, refer to "Appendix B: Power Saving."
S1C17001 TECHNICAL MANUAL
OSC
Clock source
wakeup
selection
System
Wait circuit for OSC3
clock
wakeup
OSC1
Division circuit
(1/1 to 1/4)
Division ratio
selection
S1C17 core
S1C17 core
Figure 7.1.1: OSC module configuration
Gear selection
Clock gear Gate
(1/1 to 1/8)
Gate
On/off control
Gate
On/off control
Division circuit
Gate
(1/1 to 1/16K)
Division
OSC1
(1/128)
circuit
Gate
(1/1 to 1/32)
Division ratio selection On/off control
EPSON
7 OSCILLATOR CIRCUIT (OSC)
CLG
HALT
CCLK S1C17 core
BCLK Internal bus, RAM,
ROM
HALT
ITC, T16, T8F, UART,
SPI, I2C, T16E, P,
PCLK
MISC, REMC,
Control register (CT,
SWT, WDT, T8OSC1)
PSC
T8F, T16, T16E,
REMC, P, UART, SPI,
I2C
CLK_256Hz CT, SWT, WDT
T8OSC1
55