X5341: Remc Prescaler Clock Select Register (Remc_Psc) - Epson S1C17001 Technical Manual

21 REMOTE CONTROLLER (REMC)

0x5341: REMC Prescaler Clock Select Register (REMC_PSC)

Register name Address Bit
REMC 0x5341 D7–4 CGCLK[3:0] Carrier generator clock select
Prescaler Clock (8 bits)
Select Register
(REMC_PSC)
D3–0 LCCLK[3:0] Length counter clock select
D[7:4] CGCLK[3:0]: Carrier Generator Clock Select Bits
Select a carrier generation clock from the 15 prescaler output clocks.
CGCLK[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
D[3:0] LCCLK[3:0]: Length Counter Clock Select Bits
Select a data length counter clock from the 15 prescaler output clocks.
LCCLK[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
Note: The clock should be set only while the REMC module is stopped (REMEN/REMC_CFG register
= 0).
280
Name Function
(Prescaler output clock)
(Prescaler output clock)
Table 21.7.2: Carrier generation clock selection
Prescaler output clock
Reserved
PCLK-1/16384
PCLK-1/8192
PCLK-1/4096
PCLK-1/2048
PCLK-1/1024
PCLK-1/512
PCLK-1/256
Table 21.7.3: Carrier generation clock selection
Prescaler output clock
Reserved
PCLK-1/16384
PCLK-1/8192
PCLK-1/4096
PCLK-1/2048
PCLK-1/1024
PCLK-1/512
PCLK-1/256
EPSON
Setting Init. R/W
CGCLK[3:0] 0x0 R/W
Clock
LCCLK[3:0]
0xf
reserved
0xe PCLK-1/16384
0xd PCLK-1/8192
0xc PCLK-1/4096
0xb PCLK-1/2048
0xa PCLK-1/1024
0x9 PCLK-1/512
0x8 PCLK-1/256
0x0 R/W
0x7 PCLK-1/128
0x6 PCLK-1/64
0x5 PCLK-1/32
0x4 PCLK-1/16
0x3 PCLK-1/8
0x2 PCLK-1/4
0x1 PCLK-1/2
0x0 PCLK-1/1
CGCLK[3:0] Prescaler output clock
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
LCCLK[3:0] Prescaler output clock
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
S1C17001 TECHNICAL MANUAL
Remarks
PCLK-1/128
PCLK-1/64
PCLK-1/32
PCLK-1/16
PCLK-1/8
PCLK-1/4
PCLK-1/2
PCLK-1/1
(Default: 0x0)
PCLK-1/128
PCLK-1/64
PCLK-1/32
PCLK-1/16
PCLK-1/8
PCLK-1/4
PCLK-1/2
PCLK-1/1
(Default: 0x0)