8-Bit Timer Reload Register And Underflow Cycle - Epson S1C17001 Technical Manual

12 8-BIT TIMER (T8F)

12.4 8-bit Timer Reload Register and Underflow Cycle

The reload data register T8F_TR (0x4202) is used to set the initial value for the down counter.
The initial counter value set in the reload data register is preset to the down counter if the 8-bit timer is reset or the
counter underflows. If the 8-bit timer is started after resetting, the timer counts down from the reload value (initial
value). This means this reload value and the input clock frequency. determines the time elapsed from the point at
which the timer starts until the underflow occurs (or between underflows). The time determined is used to obtain
the specified wait time, the intervals between periodic interrupts, and the programmable serial interface transfer
clock.
One-shot mode
Counter
Repeat mode
Counter
The underflow cycle can be calculated as follows:
Underflow interval = —————— [s]
clk_in: Count clock (prescaler output clo ck) frequency [Hz]
T8F_TR: Reload data (0 to 255)
Note: The UART generates a sampling clock that divides the 8-bit timer output into 1/16 divisions.
Be careful when setting the transfer rate.
128
Timer start
n n-1
Preset by timer reset
Timer start
n n-1
Preset by timer reset
Figure 12.4.1: Preset timing
T8F_TR + 1
Underflow cycle = —————— [Hz]
clk_in
Underflow
1 0
Auto preset
Underflow
1 0 n n-1
Auto preset
clk_in
T8F_TR + 1
EPSON
n
(n = reload data)
Underflow
1 0 n
Auto preset
S1C17001 TECHNICAL MANUAL