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16 STOPWATCH TIMER (SWT)
0x5023: Stopwatch Timer Interrupt Flag Register (SWT_IFLG)
Register name Address
Bit
Stopwatch
0x5023
D7–3 –
Timer Interrupt
(8 bits)
D2
Flag Register
D1
(SWT_IFLG)
D0
This register indicates the occurrence state of interrupt factors due to stopwatch timer 100 Hz, 10 Hz, and 1 Hz sig-
nals. If a stopwatch timer interrupt occurs, identify the interrupt factor (frequency) by reading the interrupt flag in
this register.
SIF* are SWT module interrupt flags corresponding to the individual 100 Hz, 10 Hz, and 1 Hz interrupts. It is set to
1 at the falling edge of each signal if SIE* (SWT_IMSK register) is set to 1. The stopwatch timer interrupt request
signal is output to the ITC at the same time. This interrupt request signal sets the stopwatch timer interrupt flag in
the ITC to 1 and generates an interrupt if the ITC and S1C17 core interrupt conditions are met.
The following processes must be performed to manage the interrupt factor occurrence state using this register.
1. Set the ITC stopwatch timer interrupt trigger mode to level trigger mode.
2. Reset the SWT module interrupt flag within the interrupt processing routine after the interrupt occurs (this also
resets the ITC interrupt flag).
SIF* is reset by writing as 1.
Note: To prevent generating unnecessary interrupts, SIF* must be reset before permitting clock timer
interrupts using SIE.*
D[7:3]
Reserved
D2
SIF1: 1 Hz Interrupt Flag
Interrupt flag indicating the 1 Hz interrupt factor occurrence status.
1(R):
Interrupt factor present
0(R):
No interrupt factor (default)
1(W):
Reset flag
0(W):
Disabled
Setting SIE1 (D2/SWT_IMSK register) to 1 sets SIF1 to 1 at the 1 Hz signal falling edge.
D1
SIF10: 10 Hz Interrupt Flag
Interrupt flag indicating the 10 Hz interrupt factor occurrence status.
1(R):
Interrupt factor present
0(R):
No interrupt factor (default)
1(W):
Reset flag
0(W):
Disabled
Setting SIE10 (D1/SWT_IMSK register) to 1 sets SIF10 to 1 at the 10 Hz signal falling edge.
D0
SIF100: 100 Hz Interrupt Flag
Interrupt flag indicating the 100 Hz interrupt factor occurrence status.
1(R):
Interrupt factor present
0(R):
No interrupt factor (default)
1(W):
Reset flag
0(W):
Disabled
Setting SIE100 (D0/SWT_IMSK register) to 1 sets SIF100 to 1 at the 100 Hz signal falling edge.
200
Name
Function
reserved
SIF1
1 Hz interrupt flag
SIF10
10 Hz interrupt flag
SIF100
100 Hz interrupt flag
Setting
–
1 Cause of
0 Cause of
interrupt
occurred
EPSON
Init. R/W
Remarks
–
–
0 when being read.
0
R/W Reset by writing 1.
interrupt not
0
R/W
occurred
0
R/W
S1C17001 TECHNICAL MANUAL
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