Epson S1C17001 Technical Manual page 250

The IILV6[2:0] interrupt level setting bit sets the SPI interrupt level (0 to 7).
The S1C17 core accepts interrupts when all of the following conditions are met:
• The interrupt enable bit is set to 1.
• The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit is set to 1.
• The SPI interrupt has a higher interrupt level set than that set for the PSR IL (interrupt level).
• No other interrupt factors having higher precedence (e.g., NMI) are present.
For detailed information on these interrupt registers and operations when interrupts occur, refer to "6 Interrupt
Controller (ITC)."
Interrupt vectors
The SPI interrupt vector numbers and vector addresses are as listed below.
Vector number: 18 (0x12)
Vector address: 0x8040
S1C17001 TECHNICAL MANUAL
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