Block Diagram - Epson S1C17001 Technical Manual

1 OVERVIEW

1-2 Block Diagram

#TEST0–5
EXCL0–2
(P16, P07, P06)
SIN, SOUT, SCLK
(P23–25)
SDI, SDO, SPICLK
(P20–22)
SDA, SCL
(P14–15)
2
CPU Core S1C17
32 bits
1 cycle
Internal RAM
(2K bytes)
16 bits
1–5 cycles
Internal ROM
(32K bytes)
Test circuit
8/16 bits
1 cycle
I/O 1 (0x4000–)
Interrupt controller
Prescaler
8-bit timer
16-bit timer
UART
SPI
2
I C
Figure 1.2.1: Block diagram
EPSON
Reset circuit
I/O 2 (0x5000–)
MISC register
8/16 bits
Oscillator/
3 cycles
Clock generator
8-bit OSC1 timer
Clock timer
Stopwatch timer
Watchdog timer
PWM & capture
timer
Remote controller
I/O port/
I/O MUX
S1C17001 TECHNICAL MANUAL
DCLK, DST2,
DSIO(P31–33)
#RESET
OSC1–2, OSC3–4
FOUT1(P13),
FOUT3(P30)
EXCL3(P27),
TOUT(P26)
REMI(P04),
REMO(P05)
P00–07, P10–17,
P20–27, P30–33