0X4102: Uart Receive Data Register (Uart_Rxd) - Epson S1C17001 Technical Manual

0x4102: UART Receive Data Register (UART_RXD)

Register name Address Bit
UART Receive 0x4102 D7–0 RXD[7:0]
Data Register (8 bits)
(UART_RXD)
D[7:0] RXD[7:0]: Receive Data
Data in the receive data buffer is read out in sequence, starting with the oldest. Received data is placed
in the receive data buffer. The receive data buffer is a 2-byte FIFO that allows proper data receipt until
it fills, even if data is not read out. If the buffer is full and the shift register also contains received data,
an overrun error will occur, unless the data is read out before receipt of the subsequent data starts.
The receive circuit includes two receive buffer status flags: RDRY (D1/UART_ST register) and RD2B
(D3/UART_ST register). The RDRY flag indicates the presence of valid received data in the receive
data buffer, while RD2B flag indicates the presence of two items of received data in the receive data
buffer.
A receive buffer full interrupt occurs when the received data in the receive data buffer reaches the num-
ber specified by RBFI (D1/UART_CTL register).
0 is loaded into RXD7 in 7-bit mode.
Serial data input via the SIN pin is converted to parallel, with the initial bit as LSB, the High level bit as 1,
and the Low level bit as 0. This data is then loaded into the receive data buffer.
This register is read-only. (Default: 0x0)
S1C17001 TECHNICAL MANUAL
Name Function
Receive data in the receive data
buffer
RXD7(6) = MSB
RXD0 = LSB
EPSON
Setting Init. R/W
0x0 to 0xff (0x7f) 0x0 R
18 UART
Remarks
Older data in the
buffer is read out
first.
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