Compare Data Settings - Epson S1C17001 Technical Manual

13 PWM & CAPTURE TIMER (T16E)

13.4 Compare Data Settings

Compare data register/buffer selection
The PWM & capture timer incorporates a data comparator allowing comparison of counter data against any
desired value. This comparison data is stored in the compare data A and B registers. Data can be read or written
directly to or from the compare data registers.
The compare data buffers enable automatic loading to the compare data registers of the comparison values set
in the buffers when the counter is reset by software (writing 1 to T16ERST) or by a compare B match signal.
The CBUFEN (D5/0x5306) is used to set which of the compare data register and buffer the comparison values
are written to.
∗ CBUFEN: Comparison Buffer Enable Bit in the PWM Timer Control (T16E_CTL) Register (D5/0x5306)
Writing 1 to CBUFEN selects the compare data buffer. Writing 0 to it selects the compare data register. The
compare data register is selected after initial resetting.
Compare data writing
Compare data A is written to T16ECA[15:0] (D[15:0]/T16E_CA register). Compare data B is written to
T16ECB[15:0] (D[15:0]/T16E_CB register).
∗ T16ECA[15:0]: Compare Data A in the PWM Timer Compare Data A (T16E_CA) Register (D[15:0]/0x5300)
∗ T16ECB[15:0]: Compare Data B in the PWM Timer Compare Data B (T16E_CB) Register (D[15:0]/0x5302)
When CBUFEN is set to 0, the compare data register values can be read or written directly by these registers.
When CBUFEN is set to 1, data is read from and written to these registers via the compare data buffers. The
buffer contents are loaded into the compare data registers when the counter is reset.
The compare data registers and buffers are set to 0x0 after initial resetting.
The timer compares the count data against the compare data registers and generates a compare match signal if
the values are equal. This compare match signal generates an interrupt and controls the clock (TOUT signal)
output externally.
Compare data B also determines the counter reset cycle.
The counter reset cycle can be calculated as follows:
Counter reset interval= ———— [s]
Counter reset cycle = ———— [Hz]
CB: Compare data B (T16E_CB register value)
clk_in: Prescaler output clock frequency
144
CB + 1
clk_in
clk_in
CB + 1
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S1C17001 TECHNICAL MANUAL