Epson S1C17001 Technical Manual page 177

14 8-BIT OSC1 TIMER (T8OSC1)
The S1C17 core accepts interrupts when the following conditions are satisfied:
• The interrupt enable bit has been set to 1.
• The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit has been set to 1.
• The 8-bit OSC timer interrupt has been set to a higher interrupt level than that set for the PSR IL (interrupt
level).
• No other interrupt factors having higher precedence (e.g., NMI) are present.
For detailed information on these interrupt control registers and operations when interrupts occur, refer to "6
Interrupt Controller (ITC)."
Note: The following processes must be performed to manage the interrupt factor occurrence state
using the T8OSC1 module interrupt flag.
1. Set the 8-bit OSC timer interrupt trigger mode to level trigger mode.
2. Reset the 8-bit OSC module interrupt flags T8OIF within the interrupt processing routine
after the interrupt occurs (this also resets the ITC interrupt flag).
Interrupt vectors
The 8-bit OSC timer interrupt vector numbers and vector addresses are listed below.
Vector number: 8 (0x08)
Vector address: 0x8020
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S1C17001 TECHNICAL MANUAL