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Level trigger mode
In level trigger mode, the ITC samples the interrupt signal continuously using the system clock rising edge. The in-
terrupt flag (EIFTx) is set to 1 if High level is detected and is reset to 0 if Low level is subsequently detected. Since
interrupt flags (EIFTx) cannot be reset by writing 1 in this mode, the interrupt signal is held at High until the inter-
rupt source module is accepted by the S1C17 core, and the interrupt signal must subsequently be cleared.
Interrupt signal from
interrupt source
Interrupt flag within ITC
Note: The S1C17001 interrupts listed below are in level trigger mode. The interrupt flag within pe-
ripheral modules must be reset (to 1) within the interrupt processing routine rather than EIFTx
• P0 port interrupt
• P1 port interrupt
• Stopwatch timer interrupt
• Clock timer interrupt
• 8-bit OSC1 timer interrupt
• PWM & capture timer interrupt
For more information on interrupt flags for resetting, refer to the peripheral module descrip-
tion.
S1C17001 TECHNICAL MANUAL
pclk
Figure 6.3.5.2: Level trigger mode
Interrupt signal set to inactive by interrupt source
EPSON
6 INITERRUPT CONTROLLER
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