Data Transfer Control - Epson S1C17001 Technical Manual

18.5 Data Transfer Control

Make the following settings before starting data transfers.
(1) Select input clock. (See Section 18.3.)
To use the internal clock, program the 8-bit timer to output the transfer clock. See Section 12.
(2) Set the transfer data format. (See Section 18.4.)
(3) To use the IrDA interface, set IrDA mode. (See Section 18.8.)
(4) Set interrupt conditions to use UART interrupts. (See Section 18.7.)
Note: Make sure the UART is halted (when RXEN/UART_CTL register = 0) before changing the above
settings.
∗ RXEN: UART Enable Bit in the UART Control (UART_CTL) Register (D0/0x4104)
Permitting data transfers
Set the RXEN bit (D0/UART_CTL register) to 1 to permit data transfers. This switches transfer circuits to en-
able transfers.
Note: Do not set the RXEN bit to 0 while the UART is sending or receiving data.
Data transfer control
To start data transmission, write the transmission data to the UART_TXD register (0x4101).
∗ UART_TXD: UART Transmit Data Register (0x4101)
The data is written to the transmit data buffer, and the transmission circuit starts sending data.
The buffer data is sent to the transmit shift register, and the start bit is output from the SOUT pin. The data in
the shift register is then output from the LSB. The transfer data bit is shifted in sync with the sampling clock
rising edge and output in sequence via the SOUT pin. Following output of MSB, the parity bit (if parity is en-
abled) and stop bit are output.
The transmission circuit includes the TDBE (D0/UART_ST register) and TRBS (D2/UART_ST register) status
flags.
∗ TDBE: Transmit Data Buffer Empty Flag in the UART Status (UART_ST) Register (D0/0x4100)
∗ TRBS: Transmit Busy Flag in the UART Status (UART_ST) Register (D2/0x4100)
The TDBE flag indicates the transmit data buffer status. This flag switches to 0 when the application program
writes data to the transmit data buffer and reverts to 1 when the buffer data is sent to the transmit shift register.
Interrupts can be generated when this flag is 1 (see Section 18.7). Subsequent data is sent after confirming that
the transmit data buffer is empty either by using this interrupt or by inspecting the TDBE flag. The transmission
buffer size is 1 byte, but a shift register is provided separately to allow data to be written while the previous
data is being sent. Always confirm that the transmit data buffer is empty before writing transmission data. Writ-
ing data while the TDBE flag is 0 will overwrite earlier transmission data inside the transmit data buffer.
The TRBS flag indicates the shift register status. This flag switches to 1 when transmission data is loaded from
the transmit data buffer to the shift register and reverts to 0 once the data is sent. Read this flag to check wheth-
er the transmission circuit is operating or at standby.
S1C17001 TECHNICAL MANUAL
EPSON
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