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end of data transfers (Generating stop condition)
To end data transfers after all data has been transferred, the I
dition. The stop condition applies when the SCL line is maintained at High and the SDA line is pulled up from
Low to High.
The stop condition is generated by setting STP/I2CM_CTL register to 1.
When STP is set to 1, the I2CM module pulls up the I
maintained at High to generates a stop condition. The I
Before STP can be set to 1, confirm that TBUSY or RBUSY is reset to 0 from 1 (this indicates that the I2CM
module has finished data transmit/receive operation) and then make the wait time longer than 1/4 of the I
clock cycle set. When generating a stop condition to the slave device with a clock stretch function, STP must be
set to 1 after data transfer (including ACK/NAK transfer) has finished and the time for the slave device to finish
clock stretching has elapsed. STP is reset to 0 when the stop condition is generated.
Continuing data transfer (Generating Repeated start condition)
To make it possible to continue with a different data transfer after data transfer completion, the I
module) can generate a repeated start condition.
The repeated start condition is generated by setting STRT/I2CM_CTL register to 1 when the I
STRT is automatically reset to 0 once the repeated start condition is generated. Slave address transmission is
subsequently possible with the I
Disabling data transfer
After the stop condition has been generated, write 0 to I2CMEN to disable data transfers. To determine whether
the stop condition has been generated, check to see if STP is automatically cleared to 0 after it is set to 1 by
polling.
When I2CMEN is set to 0 while the I
data at that point cannot be guaranteed.
Timing chart
STRT setting
PCLK
T16 Ch.2 output
SCL0
SDA0
STRT
S1C17624/604/622/602/621 TeChniCal Manual
SDA0 (output)
SCL0 (output)
Figure 20.
5.4 Stop Condition
2
C bus SDA line from Low to High with the SCL line
C bus subsequently switches to free state.
2
SDA0 (output)
SCL0 (output)
Repeated start condition
Figure 20.
5.5 Repeated Start Condition
2
C bus remaining in the busy state.
2
C bus is in busy status, the SCL0 and SDA0 output levels and transfer
Start condition
Figure 20.
5.6 Start Condition Generation
Seiko epson Corporation
2
C master (this module) must generate a stop con-
Stop condition
2
I
2
20 i
C MaSTeR (i2CM)
C
2
C master (this
2
2
C bus is busy.
C bus busy
20-5
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