Epson S1C17624 Technical Manual page 166

14.5 Counter Reset
The counter can be reset to 0 by writing 1 to T8ORST/T8OSC1_CTL register.
Normally, the counter should be reset by writing 1 to this bit before starting the count.
The counter is reset by the hardware if the counter matches compare data after the count starts.
14.6 Compare Data Settings
Compare data is written to T8OCMP[7:0]/T8OSC1_CMP register.
After an initial reset, the compare data register is set to 0x0.
The timer compares the count data against the compare data register and generates a compare match signal as well
as resets the counter if the values are equal. This compare match signal can generate an interrupt.
The compare match cycle can be calculated as follows:
Compare match interval = ————— [s]
Compare match cycle = ————— [Hz]
CMP: Compare data (T8OSC1_CMP register value)
ct_clk: Count clock frequency
When T8OSC1 is used to generate a PWM signal, the compare data determines the frequency of the output signal.
(For a discussion of PWM output, refer to Section 14.8.)
14.7 Timer Run/STOP Control
Make the following settings before starting T8OSC1.
(1) To output the PWM signal, switch the output pin function to be used for T8OSC1. Refer to the "I/O Ports (P)"
chapter.
(2) Set the count mode (one-shot or repeat mode). See Section 14.4.
(3) Select the count clock. See Section 14.3.
(4) If using interrupts, set the interrupt level and enable T8OSC1 interrupts. See Section 14.9.
(5) Reset the counter. See Section 14.5.
(6) Set the compare data. See Section 14.6.
(7) To output the PWM signal, set the PWM duty data. See Section 14.8.
T8OSC1 includes T8ORUN/T8OSC1_CTL register to control Run/Stop.
The timer starts counting when T8ORUN is written as 1. Writing 0 to T8ORUN stops the count.
This control does not affect the counter data. The counter data is retained even when the count is halted, allowing
resumption of the count from that data.
If T8ORUN and T8ORST are written as 1 simultaneously, the timer starts counting after the reset.
If the counter matches the compare data register setting during counting, a compare match signal is output and a
cause of compare match interrupt occurs. The counter is reset to 0 at the same time. If interrupts are enabled, an in-
terrupt request is sent to the interrupt controller (ITC).
If one-shot mode is set, the timer stops the count.
If repeat mode is set, the timer continues to count from 0.
S1C17624/604/622/602/621 TeChniCal Manual
CMP + 1
ct_clk
ct_clk
CMP + 1
Seiko epson Corporation
14 8-BiT OSC1 TiMeR (T8OSC1)
14-3